A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing

Ray, S. Saha; Singh, Sonal; Sengupta, Chandrayan; Ghosh, Surajeet; Sardar, Bhaskar

doi:10.1109/ants.2018.8710130

Cited by 1 publication

(1 citation statement)

References 11 publications

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“…At the same time, packet forwarding in software is a dumb operation but highly CPU-intensive. It is widely accepted that hardware is capable of performing LPM and forwarding packets at line rate with ultra-low latency [35,45]. Therefore, it is meaningful to offload the LPM-based rule table on the FPGA as an OFU logic, while the software only needs to update the table using the OFU API.…”

Section: Offloading Lpm-based Cached-rule Table For Ip Routing Accelerationmentioning

confidence: 99%

AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

et al. 2021

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Software-defined networking (SDN) has attracted much attention since it was proposed. The architecture of the SDN data plane is also evolving. To support the flexibility of the data plane, the software implementation approach is adopted. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. However, completely implementing the data plane on hardware weakens the flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput. We offloaded a cached-rule table to the proposed accelerator and tested its performance with 100 GbE traffic. Compared with the software implementation, the evaluation result shows that the throughput can achieve a 600% improvement when processing small packets and a 100% increase in large packet processing, and the latency can be reduced by about 20× and 100×, respectively, when processing small packets and large packets.

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Section: Offloading Lpm-based Cached-rule Table For Ip Routing Accelerationmentioning

confidence: 99%