A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set

Bayruns, R.; Hofstatter, E.A.; Weston, H.T.

doi:10.1109/4.32044

Cited by 11 publications

(1 citation statement)

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“…If the transistor is cut off fast, either high-speed data can be sampled and demultiplexed, or fast analog, e.g., RF, signals can be sampled. Some publications show measured results on receivers/demultiplexers based on parallel sampling which receives low-swing data at speeds up to 3.0 Gb/s in CMOS [1], [2] and NMOS [3]. And measurements on CMOS downconversion mixers up to 1.5 GHz have been reported in [4] and [5].…”

Section: Introductionmentioning

confidence: 99%

Time resolution of NMOS sampling switches used on low-swing signals

Johansson¹,

Svensson²

1998

IEEE J. Solid-State Circuits

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A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8-m transistor. We present an expression for the aperture time for an NMOS switch when the input has low swing. The switch can, under this condition, be modeled as a device that determines a weighted average over time of the input signal. The weight function is derived. The aperture time function shows that the maximum theoretical time resolution for a switch in 0.8-m standard CMOS is 21 ps (48 Gb/s). SPICE simulations agree with the theory. Transient two-dimensional (2-D) device simulations do not contradict the predicted results. Experiments on a switch made in a 0.8-m standard CMOS process show successful sampling of every thirty-second bit of a 5-Gb/s data stream. Index Terms-Aperture time, CMOS integrated circuits, highspeed integrated circuits, sample and hold circuits.

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Section: Introductionmentioning

confidence: 99%