This work presents a FinFET‐based stable, and low‐power consuming static random access memory (SRAM) bit‐cell that used eight transistors. The performance parameter of proposed feedback‐cutting 8T (FC8T) is compared with four pre‐published cell circuits, i.e., 6T, read‐decoupled 8T(8TRD), Schmitt‐trigger based 10T (10TST), and Schmitt‐trigger‐based modified 10 T (10TMST). The write power in proposed design is reduced by 1.36×/1.32×/1.88×/1.47× compared to 6T/8TRD/10TST/10TMST cells. The write and read stability of proposed design is improved by 1.15×/1.86×/1.28×/1.148× and 2.27×/1×/1.57×/1.11×, respectively. The proposed design also shows the low variability compared to other SRAM bit‐cells.