A finite element simulator for three-dimensional analysis of interconnect structures

Sabelka, R.; Selberherr, S.

doi:10.1016/s0026-2692(00)00113-0

Cited by 29 publications

(18 citation statements)

References 27 publications

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“…Previous analysis have shown a similar temperature increase when temperature dependency of material properties on nanometric scale is not considered [9,10]. Besides this temperature underestimation, the overall temperature profile and the location of the highest temperature value are consistent with experimental conditions.…”

Section: Resultssupporting

confidence: 84%

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Análisis termo-eléctrico de elementos finitos (EF) en vías de cobre nanométricas bajo tensión de alta fluencia

Oviedo

Trojman

Kauerauf

et al. 2013

Av. Cienc. Ing. (Quito)

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This paper presents the development of a thermal-electrical finite element (FE) model with the objective to analyze failure mechanisms responsible of physical degradation (void, copper silicate formation, etc.) caused by high fluence stress of 90nm copper vias for FinfET devices. Indeed in [1], this physical degradation was interpreted as a main consequence of Joule effect, however their employed model reached too low temperatures to explain the observed physical degradation. In order to confirm this, the steady-state FE model developed in this work computes the temperature increase and distribution caused by high electrical current density flowing through a copper contact, considering non-ideal thermal and electrical interfaces. In addition, a sensitivity analysis is performed as a way to identify critical failure parameters. The temperature response of the model to independent variation of electrical resistivity of studied materials, and interfacial electrical and thermal conductance between the copper contact and its diffusion barrier were obtained. The decrease of interfacial electrical conductance triggers steady-state temperatures over copper and silicate melting points and, in consequence leads to temperature high enough to explain the physical degradation.Keywords. copper nano vias, Joule heating, finite element analysis, interface electric conductivity, sensitivity analysis. ResumenEste trabajo presenta el desarrollo de un modelo termo-eléctrico de elementos finitos (EF) con el fin de analizar los mecanismos de falla responsables de la degradación física causada por alta densidad de corriente en contactos de cobre de 90 nm empleados en dispositivos FinFET. De hecho en [1], esta degradación física fue interpretada como consecuencia principal del efecto Joule, sin embargo el modelo empleado alcanzó temperaturas demasiado bajas comparadas con el daño observado. Con el propósito de confirmar esta hipótesis, el modelo de EF de estado estable desarrollado en este trabajo calcula el incremento y la distribución de temperatura causada por alta densidad de corriente eléctrica fluyendo a través de un contacto de cobre, tomando en cuenta interfaces eléctricas y térmicas no idealizadas. Además, un análisis de sensibilidad fue realizado como un medio para identificar parámetros críticos de falla. La respuesta del modelo ante la variación independiente de la resistividad eléctrica de los materiales estudiados, y las conductancias eléctricas y tér-micas entre el contacto de cobre y su barrera de difusión fue obtenida. La disminución de la conductancia eléctrica de dicha interfaz desencadenó temperaturas de estado estable superiores a los puntos de fusión del cobre y los silicatos del contacto y, en consecuencia, permite explicar la degradación física observada.Palabras Clave. nano contactos de cobre, calentamiento Joule, análisis de elementos finitos, conductividad eléctrica de interfaz, análisis de sensibilidad.

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Section: Resultssupporting

confidence: 84%

“…Due the reduced scale of the contact, the effect of convection and radiation processes are negligible (Figure 3). Similar models developed in previous research showed good fit between experimental and simulation results for less extreme current densities [9,10].…”

Section: Model Inputssupporting

confidence: 69%

Análisis termo-eléctrico de elementos finitos (EF) en vías de cobre nanométricas bajo tensión de alta fluencia

Oviedo

Trojman

Kauerauf

et al. 2013

Av. Cienc. Ing. (Quito)

View full text Add to dashboard Cite

show abstract

“…The integration in (2) is performed only within the classical turning points. For electrostatic analysis the Smart-Analysis-Package (SAP) [9] was used. Since we focus on the subthreshold behavior of CNTFETs, we neglect charge on the CNT, which is considered to be a good approximation for the off-state regime [3,5,6,10].…”

Section: Introductionmentioning

confidence: 99%

Three-Dimensional Analysis of Schottky Barrier Carbon Nanotube Field Effect Transistors

Pourfath

Ungersboeck

Gehring

et al. 2004

Simulation of Semiconductor Processes and Devices 2004

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Two-dimensional (2D) and three-dimensional (3D) electrostatic analyses of Schottky barrier carbon nanotube field effect transistors (CNTFETs) are carried out. Comparisons between 2D and 3D simulation results for symmetric and asymmetric structures indicate that 2D simulations do not describe the behavior of the device accurately, suggesting that to understand and improve the behavior of CNTFETs 3D electrostatic analysis is required.

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“…Sabelka and Selberherr [4] modelled the via resistance of a copper via and found the measured experimental value to be 30% larger than that determined by their finite element model. They attributed this difference to the fact that they did not account for the ohmic contact interfaces in their via model.…”

Section: Introductionmentioning

confidence: 88%

“…This would account for some of the error observed ref. [4] where such interfaces were not modelled. Further resistance will be due to the presence of the interface ρ c2 .…”

Section: A Variation In Via Resistancementioning

confidence: 99%

Finite Element Modeling of Misalignment in Interconnect Vias

Holland

Reeves

Matthews

et al.

Conference on Optoelectronic and Microelectronic Materials and Devices, 2004.

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Abstract-Electrical resistance and hence heat generation in semiconductor chips are becoming more significant issues particularily as generations of silicon devices continue to have smaller features. The resistance of interconnect vias is a significant source of heat generation because of the increasing number of these on chips and increases in via resistance due to reduced size. Finite element modeling of voltage drops and current flow through interconnect vias gives information to aid in designing geometry and materials used in forming vias. It can also be used for modeling the thermal distribution in a via and hence the contribution by vias to heating a chip. In this paper we examine the effect of misalignment of the via between the two metal layers M1 and M2 with regard to the interconnect via resistance. The effect of the interface specific contact resistance is examined in particular. Significant misalignment can be tolerated without increasing the via resistance. The heat generation due to electrical current flow in the via materials and interfaces is modelled using the samefinite element mesh and software. The output of the electrical analysis is used as the heat generation input for the therml analysis.

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A finite element simulator for three-dimensional analysis of interconnect structures

Cited by 29 publications

References 27 publications

Análisis termo-eléctrico de elementos finitos (EF) en vías de cobre nanométricas bajo tensión de alta fluencia

Análisis termo-eléctrico de elementos finitos (EF) en vías de cobre nanométricas bajo tensión de alta fluencia

Three-Dimensional Analysis of Schottky Barrier Carbon Nanotube Field Effect Transistors

Finite Element Modeling of Misalignment in Interconnect Vias

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