A First Analysis of a Dynamic Memory Allocation Controller (DMAC) Core

Euro-Par 2013: Parallel Processing Workshops

2014

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While FPGA and other reconfigurable technologies have dramatically increased in size and speed, memory technology has had only modest improvements. Relative to logic speeds, memory latency is virtually flat and physical constraints on external pins limit memory bandwidth. Unfortunately, the traditional cache hierarchy found in fixedfunction integrated circuits has evolved to support sequential processors and is ineffective for highly parallel architectures.This paper proposes a novel memory subsystem and computational model for reconfigurable architectures. It envisions a system where computational cores are oversubscribed with atomic tasks and the memory subsystem enables (1) hiding of latency by enabling the cores to overlap computation and memory transactions and (2) the system to fully utilize the available memory bandwidth. The first step in this grand vision is to change the memory model. Instead of a byte-addressable, global address space, a named segment memory controller is introduced and an FPGA-based implementation presented in this paper.

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Section: Theory Of Operationmentioning

confidence: 98%

A Novel Memory Subsystem and Computational Model for Parallel Reconfigurable Architectures

Euro-Par 2013: Parallel Processing Workshops

2014

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“…In an effort to address this issue, we began investigating ways to improve memory bandwidth and reduce memory latency. This led to the implementation of a Dynamic Memory Allocation Controller (DMAC) [22]. The DMAC is a message-store unit that can handle variable number of variable-sized memory segments, independent of any software process or OS involvement.…”

Section: B Proposed Exascale Research Toolsmentioning

confidence: 99%

Architecture and Applications for an All-FPGA Parallel Computer

2012 41st International Conference on Parallel Processing Workshops

2012

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The Reconfigurable Computing Cluster (RCC) project has been investigating unconventional architectures for high end computing using a cluster of FPGA devices connected by a high-speed, custom network. Most applications use the FPGAs to realize an embedded System-on-a-Chip (SoC) design augmented with application-specific accelerators to form a message-passing parallel computer. Other applications take a single accelerator core and tessellate the core across all of the devices, treating them like a large virtual FPGA. The experimental hardware has also been used for basic computer research by emulating novel architectures. This article discusses the genesis of the over-arching project, summarizes results of individual investigations that have been completed, and how this approach may prove useful in the investigation of future Exascale systems.

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Architecture and applications for an All-FPGA parallel computer

2013

Cluster Comput