A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm

Sani, Awais; Coussy, Philippe; Chavet, Cyrille

doi:10.1109/tsp.2013.2264057

Cited by 19 publications

(17 citation statements)

References 30 publications

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“…For solving collision problem, the existing solutions can be categorized into two families. The first family includes solutions like [10][11][12][13][14] in which the problem is solved without any changes in the standard architecture; i.e., these approaches use a standard network/memory. In [10], that is proposed with the network option but limited to certain codes.…”

Section: State Of the Artmentioning

confidence: 99%

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Architecture for Collision‐Free Communication Using Relaxation Technique

Rehman

Akhtar

Khan

et al. 2018

Wireless Communications and Mobile Computing

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In today’s world we are surrounded by world of smart handheld devices like smart phones, tablets, netbooks, and others. These devices are based on advance technologies of multiple-input and multiple-output, Orthogonal Frequency Division Multiplexing (OFDM), and advance data reliability techniques such as forward error corrections. High data rates are among the requirements of these technologies for which turbo and low density parity check codes (LDPC) are widely used in these standards. In order to get high speed, we need multiple and parallel processors for the implementation of such codes. But there exists a collision problem as a consequence of parallel processor. This problem results in increase latency and increase of hardware complexity. In this work an approach for collision problem is presented in which network relaxation technique is used which is based on a fast clique detection. The proposed approach results in high throughput in terms of latency and complexity. Furthermore, the proposed solution is able to solve the collision problem by connecting network optimization for achieving high throughput.

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Section: State Of the Artmentioning

confidence: 99%

“…Metaheuristics approach [12] overcame this limitation but not the polynomial time. The polynomial is introduced in [13].…”

Section: State Of the Artmentioning

confidence: 99%

Architecture for Collision‐Free Communication Using Relaxation Technique

Rehman

Akhtar

Khan

et al. 2018

Wireless Communications and Mobile Computing

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“…Internal memory mapping has long been used in non-spatial data processing (Chen et al 2010;Sani et al 2013). For spatial data, especially in mobile GIS, internal memory mapping can improve the rendering time efficiency.…”

Section: Data Memorymentioning

confidence: 99%

Efficient rendering of natural hazards data in mobile GIS

Xia

Dong

Tanida³

2015

Geomatics, Natural Hazards and Risk

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Mobile GIS can be valuable tools for emergency managers and first responders. For time critical applications, such as natural disaster management and response, efficient rendering of spatial data is essential. This letter introduces several methods that have been implemented as new mobile GIS tools for efficient rendering of natural hazard data, including double-buffering, multi-level memory buffering, local updating, patch rendering, interruptible rendering, data memory, and raster rendering. The time cost of each operation is obtained through experiments. Examples of data rendering for geological hazard and risk assessment are also provided.

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“…these approaches use an architecture without making any changes to it (e.g. [10][11] [13] or [16]). A solution is proposed in [10] to solve the memory mapping problem under network constraint.…”

Section: Related Workmentioning

confidence: 99%

“…Of course, this results in oversized memory architecture to store data. Authors of [16] use a dual-access memory mapping approach in order to map the data in minimum number of memory banks. The approach has been developed using polynomial time algorithm to target both Turbo and LDPC codes.…”

Section: Related Workmentioning

confidence: 99%

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures

Reehman

Coussy

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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Parallel hardware architectures are needed to achieve high throughput systems. Unfortunately, efficient parallel architectures require removing memory access conflicts. This is particularly true when designing turbo-codes, channel interleaver or LDPC (Low Density Parity Check) codes architectures which are one of the most critical parts of parallel decoders. Many solutions are proposed in state of the art to find conflict free memory mapping but they are either limited to a subset of constraints, or result in high architectural cost. These drawbacks come from the interleaving law and the incompatibility between this law and the targeted interconnection network (in coder/encoder architecture). In this paper we propose a conflict free memory mapping approach that is able to generate optimized hardware architectures by limiting these drawbacks. The proposed solution constructs a customized interconnection network by analyzing data access patterns defined in the interleaving law. Our approach is then compared to state of the art methods and its interest is shown through the design of parallel interleavers for HSPA.

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A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm

Cited by 19 publications

References 30 publications

Architecture for Collision‐Free Communication Using Relaxation Technique

Architecture for Collision‐Free Communication Using Relaxation Technique

Efficient rendering of natural hazards data in mobile GIS

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures

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