A flash-TDC hybrid ADC architecture

Single-slope analog-to-digital converter (SS ADC) and time-to-digital converter (TDC) architectures in their high-speed or high-resolution status tend to either have high-power consumption or occupy large area. However, using the hybrid structure of these two, although synchronizing them might be a limiting factor, can solve the area and power consumption issues. In this paper, a 4-bit SS ADC is combined with a 4-bit TDC. Moreover, a new low-powered continuous-time comparator architecture is designed to adjust its current based on not only the inputs amplitude but also their proximity near the flip point. In addition, a novel delay correction technique is utilized to resolve its nonlinear propagation delay. The presented technique reduces 90% nonlinearity of the comparator’s propagation delay and decreases its delay variation to 450[Formula: see text]ps. Using TSMC CMOS 130[Formula: see text]nm technology with a sampling frequency of 5.88[Formula: see text]MHz, the simulation result illustrates 788[Formula: see text][Formula: see text]W power consumption with the master clock frequency of 100[Formula: see text]MHz while an integral nonlinearity (INL) of [Formula: see text]1.41–+0.76[Formula: see text]LSB and a differential nonlinearity (DNL) of [Formula: see text]1.05–+0.05[Formula: see text]LSB is achieved in 625[Formula: see text]ps resolution. Finally, figure-of-merit (FoM) depicts 31.2[Formula: see text]fJ/conv. step. The presented converter can be used in CMOS image sensors and multi-resolution applications.

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A flash-TDC hybrid ADC architecture

Cited by 2 publications

References 7 publications

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An 8-bit Hybrid TDC/Single-Slope ADC with an Improved Continuous-Time Comparator

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