A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems

Abstract

In this paper, we propose a flexible and high-reliable HW/SW co-design method for real-time systems consisting of multiple functional modules using general purpose components such as DSP, CPU and memory. In our method, we specify a system as a parallel composition of concurrent periodic EFSMs with timing constraints. As communication primitives among EFSMs, multi-way synchronization mechanism can be specified. Here, we propose a technique for efficient development of real-time embedded systems considering both reliability and cost-performance. For the purpose, using a parametric model checking technique, we derive a parameter condition which must hold for the system to proceed without deadlocks and satisfy given timing constraints. Based on the derived parameter condition and cost-performance characteristic of available components, an appropriate combination of components is automatically selected so that the total cost is minimized. We have developed a design support tool based on the proposed technique. By applying our method to development of a basic functionality of a cellular phone, we could decide which functional modules should be implemented as dedicated HW units or on-chip-CPUs' software, and select suitable DSPs and memories with low costs.

Implementation of Simulation Algorithms in FPGA for Real Time Simulation of Electrical Networks with Power Electronics Devices

“…Concurrent periodic Extended Finite Sate Machines ("EFSMs") are used in distributed real time systems as a formal representation of concurrent process [4]. We have modeled the PEs as a parallel composition of concurrent periodic EFSMs synchronized by a scheduler.…”

“…TSI to TSn -Multiple time step synchronizing signals; STC_1 to STC_n -The PE inputs are sampled when a STC for the module is asserted; REG_1 to REG_n -Asserted at the end of each timestep to store the newly computed result at the output registers of the PE; EOC_1 to EOC_n -Tells the scheduler all PEs completed their processing before the end of the timestep. An EFSM is defined as 6-tuple where the sixth element of the tuple is a counter holding the elapsed time since it has moved to a new state [4]. Because the devices modeled here do not use elapsed time we removed it from the PE EFSM representation.…”

“…The transition rules are represented as a logical conjunction of integer linear inequalities on the variables. The EFSMs are made periodic by introducing a dummy transition as the last event of a path starting at the initial state so that it returns to the initial state [4]. In order to execute an event a the value of the associated transition rule P must be true.…”

“…Input events are represented as a?x and output events are represented as b!y{y := E(x)} where x and y denote input and output variables, respectively. b!y( {y:=E(x)}[P] denotes that the output event b is executed at the end of the time step satisfying P and its output value y is E(x) [4]. This notation will be used in the following sections to describe PEs.…”

“…Besides, it consumes little hardware so that we chose to implement the Adams-Bashforth-2 extrapolation rule [13] [14]. We can rearrange its interactive equation to use only addition, subtraction and shift operations: k1 = f(x(n),y(n))+O.5 f(x(n),y(n)), (3) k2= k1-O.5 f(x(n -1),y(n -1)), (4) y(n + 1) = y(n) + k2 *AT,…”