A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate

Vezyrtzis, Christos; Jiang, Weiwei; Nowick, Steven M.; Tsividis, Y.

doi:10.1109/jssc.2014.2336532

Cited by 16 publications

(11 citation statements)

References 26 publications

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“…Also, a few CT-DSP silicon prototypes have been fabricated in domains like audio [24], [33] and RF [14], showing significant promise. As an example, a prototype first-generation CT DSP [24] demonstrated comparable total dynamic power to an industrial DSP design [18], for typical speech signals.…”

Section: B Prior Work: Ct Dsps and Adaptive Delay Linesmentioning

confidence: 99%

“…The cell throttles its input channel until the charging capacitor is fully discharged; this operation is not shown in Fig. 5 but is thoroughly described in [33]. The status signal BU SY is asserted high during the entire active phase, reporting an occupied cell.…”

Section: A Delay Linementioning

confidence: 99%

“…To compensate for this variability, the number of delay cells within one segment is fine-tuned in a digital fashion. In [33], this leads to a worst case mismatch of up to ±1%. More details on tuning can be found in [33].…”

Section: A Delay Linementioning

confidence: 99%

“…In [33], this leads to a worst case mismatch of up to ±1%. More details on tuning can be found in [33].…”

Section: A Delay Linementioning

confidence: 99%

“…As a concrete case study, we focus on the use of the delay lines in a recently introduced type of signal processors called continuous-time digital-signal processors (CT DSPs), in such systems, the delay line can contribute up to 70% of the total power [24], [33]. However, our method is expected to have applicability to many other domains.…”

Section: Introductionmentioning

confidence: 99%

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Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity

Vezyrtzis

Tsividis

Nowick

2015

IEEE Trans. VLSI Syst.

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A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst case input rate. However, due to their rigid structure, they have suboptimal energy for low-and varyingrate input streams. We introduce a complete methodology for designing reconfigurable delay lines that dynamically adapt their granularity to actual input traffic, on-the-fly, without stalling or disturbing normal operation. Two or more modes can be used, with different granularities to handle different traffic densities. During sparser traffic, the system is reconfigured to the proper coarser-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is one promising domain, continuous-time digital signal processors (CT DSPs), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. Design approaches for bimodal and trimodal adaptive lines are presented, which are then implemented in a 0.13-µm IBM CMOS technology. Simulations for these delay lines demonstrate savings in overall dynamic power up to 45.5% and 71.1%, respectively, when compared with a nonadaptive design, with only minimal area overhead (1.5% and 3%, respectively, for a targeted configuration). Using extensions to more configuration modes, further power reductions can be achieved. While results are presented for CT DSPs, significant benefits are also expected in many other domains, where the delay lines are used.Index Terms-Asynchronous systems, delay line, digital design, digital signal processor (DSP). 1063-8210

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