A Flexible Hardware Architecture for Wavelet Packet Transform With Arbitrary Tree Structure

Abstract

We present a new hardware architecture for implementing the orthogonal wavelet packet transform with an arbitrary wavelet tree. The architecture is flexible enough to accommodate an arbitrary wavelet filter and an arbitrary tree up to a certain depth. The tree structure is specified through an efficient register parameterization architecture. We provide a detailed description of the different modules and complexity estimates for the application-specified integrated circuit implementation of the proposed architecture.Index Terms-Application-specified integrated circuit (ASIC), sensor compression, wavelet packets, wavelet tree.

FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters

“…To increase the performance, in [21] a VLSI architecture of DWPT was presented which based on frame-partition architecture. In [22], authors implemented a flexible architecture of DWPT and IDWPT based on register interface and a multiplexing structure.…”

A Novel Ultra High Speed and Configurable Discrete Wavelet Packet Transform Architecture

“…In 2006, [9] presented a wordserial pipeline architecture with a new parallel FIR filter processor to perform the DWPT/IDWPT transform. And between the years 2013-2014, [10] presented a flexible architecture of DWP/IDWPT based directly on the registers and on an efficient multiplexing structure.…”

“…However, DWPT (based of FIR filter banks) complexity makes it hard to fulfill high throughput and low area (Material resource) consumption. To provide these constraints, we find many works dedicated of the implementation of DWPT on FPGA like [3][4][5][6][7][8][9][10][11][12][13][14][15][16].…”