A flexible HEVC intra mode decision hardware for 8kx4k real time encoder

Lu, Yanheng; Cheng, Wei; Huang, Leilei; Zeng, Xiaoyang; Fan, Yibo

doi:10.1109/asicon.2015.7517190

Cited by 4 publications

(7 citation statements)

References 4 publications

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“…It takes 1728 cycles to compute the direction of all 4 × 4 blocks in a CTU, which can meet the requirement of 8K × 4K@46 fps real-time encoding. The speed is significantly improved compared to [29,30]. Meanwhile, the hardware takes 2094 total gate count, which is a little more than the architecture which takes 1659 gates in [24].…”

Section: Synthesis Resultsmentioning

confidence: 99%

Fast algorithm for HEVC intra‐coding implemented by preprocessing

Xu³

et al. 2019

IET Image Processing

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Section: Synthesis Resultsmentioning

confidence: 99%

Fast algorithm for HEVC intra‐coding implemented by preprocessing

Xu³

et al. 2019

IET Image Processing

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“…Its gate count is 14.9k and maximum operating speed is 2GHz. Gate count increased by 75%, Maximum processing speed increased from 622MHz to 2GHz prepared to best performance of existing hardware structure, Lu [2]. Table 2 compares the hardware implementation results with other structures.…”

Section: Implementation Resultsmentioning

confidence: 99%

Hardware Design of Intra Prediction Angular Mode Decision for HEVC Encoder

Choi¹,

A.N²,

Ryoo³

2016

Advanced Science and Technology Letters

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In this paper, we propose a hardware design of intra prediction angular mode decision for HEVC encoder. The intra prediction of HEVC includes a total of 35 modes and has better coding performance than H.264/AVC. However, high computational complexity and computation time are required to process all 35 modes. Therefore, this paper proposes a hardware structure using an efficient angular mode decision algorithm by the simple operation using the difference of the original pixel and its position. The hardware architecture of this paper reduces computation time by parallel processing from 4x4 block size to 64x64 block size. In this paper, we use a minimized arithmetic unit by determining the angular mode by predicting the direction through a simple operation unlike the existing structure. The proposed hardware architecture was designed using Verilog HDL, implemented on a 65nm technology, synthesized with Synopsys design compiler. Synthesized gate count amounted to 14.9K and the maximum operating frequency at 2GHz.

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“…The gate number is 14.9K and the maximum operating frequency is 2GHz. Finally, compared with Lu [9], which has better performance than the existing structure, the area is reduced by 75% and the maximum operating frequency is increased from 622MHz to 2GHz.…”

Section: Resultsmentioning

confidence: 99%

“…The synthesis result shows that the gate count is 14.9K and the maximum operating frequency is 2GHz. The hardware structure of this paper is compared with Lu [9], which has the best results in terms of the number of gates and the maximum operating frequency in the comparative paper. As a result, the number of gates decreased by 75% and the maximum operating frequency increased from 622MHz to 2GHz.…”

Section: Implementation Resultsmentioning

confidence: 99%