are the minimum processing units that connected by synapses, the essential components to perform various basic brain functions, like computing, learning, memorizing, integrating, and transmitting the stimulus from outside world. [4] Both two-terminal memristors and three/multi terminal transistors are promising candidates for artificial synapse, in which the synaptic weight update is mimicked by the conductance switching. [5][6] The achieving of distinct states of multi-level conductance is significant for the mimicking of efficient synaptic functionalities. [7] It is determined mainly by the switching dynamic range and the linearity, but the former is limited in energy-efficient synaptic devices. The linearity of conductance switching is noteworthy; however, the challenges remain unsolved under low voltage spiking operation. [7][8][9] Synaptic transistor provides a parallel "write" and "read" operation through the gating of channel conductance by the dielectrics, including electret, ferroelectric, ionic, and floating gate, etc. [10][11][12][13][14][15][16] Accordingly, it has the ability of completing the signal transmission and learning process synchronously for the simulating of synaptic functionalities. [17] Charge storage dielectrics have attracted considerable attention in synaptic transistors, due to the rich material sources, simple procedure, and wide process window. [18] However, the accumulated charges (holes/electrons) tend to be dissipated quickly after low-voltage operations, and reach a saturation state with improved voltages, which lead to the nonlinear behavior of the conductance switching. [11,19] The demanded nonvolatile and reliable multi-level date storage Synaptic transistors have shown great potential in neuromorphic computing, but remain challenging to simulate linear weight updates through conductance switching under low voltage spiking operation. Here, a low voltage and near-linear weight update synaptic transistor are proposed by developing an interfacial-defect dominated floating gate structure, in which inter-diffused defects are surrounded by near-defect free and ultrathin (1 nm) dielectrics in HfO 2 /Al 2 O 3 periodic high-k laminates. In the laminates, inter-diffused defects are surrounded by near-defect free and ultrathin (1 nm) HfO 2 and Al 2 O 3 tunneling layers deposited by atom layer deposition, which contributes to the accurate regulation of multi-level charge trapping confined at independent interfacial regions, and trades off the low operation voltages and the nonvolatile characteristics of the devices. A very small conductance switching nonlinearity (NL = 0.05) and an excellent image recognition accuracy (93.1%) are demonstrated under low voltages (−3 V/1.8 V) in an optimized device with (1 nm HfO 2 /1 nm Al 2 O 3 ) 3 laminates. Besides, the basic synaptic functions are successfully mimicked based on the long-term plasticity. These results have referential significance for the future artificial synapse with low energy consumption and high efficiency.