A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers

Abstract

Global navigation satellite system (GNSS) technology is evolving at a rapid pace. The rapid advancement demands rapid prototyping tools to conduct research on new and innovative signals and systems. However, researchers need to deal with the increasing complexity and integration level of GNSS integrated circuits (IC), resulting in limited access to modify or inspect any internal aspect of the receiver. To address these limitations, the authors designed a low-cost System-on-Chip Field-Programmable Gate Array (SoC-FPGA) architecture for prototyping experimental GNSS receivers. The proposed architecture combines the flexibility of software-defined radio (SDR) techniques and the energy efficiency of FPGAs, enabling the development of compact, portable, multi-channel, multi-constellation GNSS receivers for testing novel and non-standard GNSS features with live signals. This paper presents the proposed architecture and design methodology, reviewing the practical application of a spaceborne GNSS receiver and a GNSS rebroadcaster, and introducing the design and initial performance evaluation of a general purpose GNSS receiver serving as a testbed for future research. The receiver is tested, demonstrating the ability of the receiver to acquire and track GNSS signals using static and low Earth orbit (LEO)-scenarios, assessing the observables’ quality and the accuracy of the navigation solutions.

Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform

“…The HS-GNSS receiver outlined in this paper is implemented using the SoC-FPGA receiver architecture presented in [ 21 ]. Comprehensive details of the proposed architecture can be found in the same reference, with only a brief overview provided here.…”

“…The observables include pseudorange, carrier phase, and Doppler shifts. The SoC FPGA architecture and design methodology is explained in detail in [ 21 ]. The GNSS-SDR software receiver is explained in detail in [ 25 , 26 ].…”

“…To integrate the high-sensitivity capabilities, significant modifications were made to the SoC-FPGA receiver architecture presented in [ 21 ]. These modifications included the implementation of a new acquisition hardware accelerator in the FPGA and modifications to the GNSS-SDR software receiver.…”

“…The proposed design is based on the SoC-FPGA receiver architecture introduced in [ 20 , 21 ]. In the presented work, the authors upgraded this architecture and developed a concept demonstrator implementing high sensitivity mode.…”

“…A brief description of the SoC-FPGA receiver architecture is also provided. A more detailed description of the SoC-FPGA receiver architecture and design methodology can be found in [ 21 ].…”