A Floating-point Coprocessor Configured by a FPGA in a Digital Platform Based on Fixed-point DSP for Power Electronics

Hu, Haibing; Jin, Tianjun; Zhang, Xianmiao; Liu, Zhengyu; Qian, Zhaoming

doi:10.1109/ipemc.2006.4778177

2006 CES/IEEE 5th International Power Electronics and Motion Control Conference 2006

DOI: 10.1109/ipemc.2006.4778177

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A Floating-point Coprocessor Configured by a FPGA in a Digital Platform Based on Fixed-point DSP for Power Electronics

Haibing Hu¹,

Tianjun Jin²,

Xianmiao Zhang³

et al.

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Cited by 3 publications

References 5 publications

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Rapid Construction of a 100KW three-level Inverter for Synchronous Motor Based on a Universal Digital Platform, Software Building Blocks and PEBBs

Yao

Chen

et al. 2007

APEC 07 - Twenty-Second Annual IEEE Applied Power Electronics Conference and Exposition

Self Cite

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This paper presents a new method for rapidly constructing a 1OOKW three-level inverter for synchronous motor using three basic elements: a universal digital platform, software building blocks and Power Electronic Building Blocks(PEBB). The universal digital platform is designed based on DSP and FPGA(Field Programmable Gate Array), which aims for use in medium-or high-power applications. Software modules, which are encapsulated with specific functions using c-code, are used to assemble the control software. Equipped with a driver board, the cooling system and power devices, the power modules are used to build the main circuit. Taking advantages of these three elements, the power electronic system can be configured with a significant reduction in development time and effort.

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Rapid Construction of a 100KW three-level Inverter for Synchronous Motor Based on a Universal Digital Platform, Software Building Blocks and PEBBs

Yao

Chen

et al. 2007

APEC 07 - Twenty-Second Annual IEEE Applied Power Electronics Conference and Exposition

Self Cite

View full text Add to dashboard Cite

show abstract

Realization of FIR filter using high speed, low power floating point arithmetic unit

Immareddy¹,

Talusani²,

Rao³

2015

2015 International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO)

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Power optimization of single precision floating point FFT design using fully combinational circuits

Ghate

Gurjar

Ghate³

2013

2013 15th International Conference on Advanced Computing Technologies (ICACT)

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This paper focused on the design of 32 bit IEEE 754 single precision floating point architecture for 8 point FFT. The total design is in combinational form. The FFT design is simulated in Active HDL. Results are verified with MATLAB simulation. Correctness is obtained up to twenty two bit. The design is tested for complex input data (separately for real and imaginary data). For low power design pipelining is used i.e. forward path cutset to FFT stages. Using two stages pipelining, the power of architecture is calculated in Design Vision tool of Synopsys by 45nm technology file. By this scheme, the total power required is reduce up to 35%.

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A Floating-point Coprocessor Configured by a FPGA in a Digital Platform Based on Fixed-point DSP for Power Electronics

Cited by 3 publications

References 5 publications

Rapid Construction of a 100KW three-level Inverter for Synchronous Motor Based on a Universal Digital Platform, Software Building Blocks and PEBBs

Rapid Construction of a 100KW three-level Inverter for Synchronous Motor Based on a Universal Digital Platform, Software Building Blocks and PEBBs

Realization of FIR filter using high speed, low power floating point arithmetic unit

Power optimization of single precision floating point FFT design using fully combinational circuits

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