A Floating-Point Extended Kalman Filter Implementation for Autonomous Mobile Robots

Bonato, Vanderlei; Marques, Eduardo; Constantinides,

doi:10.1109/fpl.2007.4380720

Cited by 14 publications

(13 citation statements)

References 7 publications

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“…The Extended Kalman Filter (EKF) dynamically linearizes the system equations to allow application of the KF equations (algorithm 2.2) [11][12][13][14]. The EKF is not optimal because the system must be linearized about the current state estimate.…”

Section: Assumptionsmentioning

confidence: 99%

“…Particularly, hardware implementations of KFs have been shown to dramatically improve performance [8,[18][19][20]. Just applying C to HDL methods have shown to be relatively inefficient [14,19].…”

Section: Kf and Ekf Hardware Architecturesmentioning

confidence: 99%

“…There have been some implementations of linear KFs on FPGAs in the literature [7,14,21], but these do not extensively address some of the limitations of specific features of the FPGA platform such as microprocessor or memory interfaces. Due to the inclusion of nonlinear functions and linearization, the EKF is more difficult to efficiently implement in hardware [13,19,22].…”

Section: Kf and Ekf Hardware Architecturesmentioning

confidence: 99%

See 2 more Smart Citations

Dynamically reconfigurable systolic array accelerators: a case study with extended Kalman filter and discrete wavelet transform algorithms

Sudarsanam

Barnes

Carver

et al. 2010

IET Comput. Digit. Tech.

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Section: Assumptionsmentioning

confidence: 99%

Section: Kf and Ekf Hardware Architecturesmentioning

confidence: 99%

Section: Kf and Ekf Hardware Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

Dynamically reconfigurable systolic array accelerators: a case study with extended Kalman filter and discrete wavelet transform algorithms

Sudarsanam

Barnes

Carver

et al. 2010

IET Comput. Digit. Tech.

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“…Here, x ij is equal to one if and only if option OP ij is selected for the reference A i . Finally, equation (3) indicates that exactly one option is chosen for each reference.…”

Section: Formulation Of the Data Reuse Exploration Problemmentioning

confidence: 99%

“…This is because FPGAs with heterogeneous hardware resources successfully fill the gap between microprocessors and ASICs [1]. FPGAs could achieve higher performance and more efficient power consumption than microprocessors [2], [3]. Meanwhile, FPGAs keep higher flexibility and programmability than ASICs, although consume 9-12 times more power [4].…”

Section: Introductionmentioning

confidence: 99%

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Liu

Constantinides

Masselos

et al. 2009

IET Comput. Digit. Tech.

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Contemporary FPGA-based reconfigurable systems have been widely used to implement data dominated applications. In these applications data transfer and storage consume a large proportion of the system energy. Exploiting data reuse can introduce significant power savings, but also introduces the extra requirement for on-chip memory. To aid data reuse design exploration early during the design cycle, we present an optimization approach to achieve a power-optimal design satisfying an on-chip memory constraint in a targeted FPGA-based platform. The data reuse exploration problem is mathematically formulated and shown to be equivalent to the Multiple-Choice Knapsack Problem (MCKP). The solution to this problem for an application code corresponds to the decision of which array references are to be buffered on-chip and where loading reused data of the array references into on-chip memory happens in the code, in order to minimize power consumption for a fixed on-chip memory size. We also present an experimentally verified power model, capable of providing the relative power information between different data reuse design options of an application, resulting in a fast and efficient design space exploration. The experimental results demonstrate that the approach enables us to find the most power efficient design for all the benchmark circuits tested.

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HW/SW co-design of a visual SLAM application

Piat

Fillatreau

Tortei

et al. 2018

J Real-Time Image Proc

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Vision-based advanced driver assistance systems (ADAS), appeared in the 2000s, are increasingly integrated on-board mass-produced vehicles, as off-the-shelf low-cost cameras are now available. But ADAS implement most of the timespecific and basic functionalities such as lane departure or control of the distance to other vehicles. Integrating accurate localization and mapping functionalities meeting the constraints of ADAS (high-throughput, low-consumption, and smalldesign footprint) would pave the way towards obstacle detection, identification and tracking on-board vehicles at potential high speed. While the SLAM problem has been widely addressed by the robotics community, very few embedded operational implementations can be found, and they do not meet the ADAS-related constraints. In this paper, we implement the first 3D monocular EKF-SLAM chain on a heterogeneous architecture, on a single System on Chip (SoC), meeting these constraints. In order to do so, we picked up a standard co-design method (Shaout et al. Specification and modeling of hw/sw co-design for heterogeneous embedded systems, 2009) and adapted it to the implementation of potentially any of such complex processing chains. The refined method encompasses a hardware-in-the-loop approach allowing to progressively integrate hardware accelerators on the basis of a systematic rule. We also have designed original hardware accelerators for all the image processing functions involved, and for some algebraic operations involved in the filtering process.

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A Floating-Point Extended Kalman Filter Implementation for Autonomous Mobile Robots

Cited by 14 publications

References 7 publications

Dynamically reconfigurable systolic array accelerators: a case study with extended Kalman filter and discrete wavelet transform algorithms

Dynamically reconfigurable systolic array accelerators: a case study with extended Kalman filter and discrete wavelet transform algorithms

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

HW/SW co-design of a visual SLAM application

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