A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Abstract

Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumption, modern microprocessor designers or researchers propose and apply aggressive power-saving techniques in the form of clock-gating and/or power-gating in order to operate the processor within a given power envelope. These techniques, however, often lead to high-frequency current variations, which can stress the power delivery system and jeopardize reliability due to inductive noise (L di dt ) in the power supply network. To counteract these issues, modern microprocessors are designed to operate under the worst-case current assumption by deploying adequate decoupling capacitance. With the trend of lower supply voltage and increased leakage power and current consumption, designing a processor for the worst case is becoming less appealing.In this paper, we propose a new dynamic inductive-noise controlling mechanism at the microarchitectural level that will limit the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt controller is the first that takes the processor's floorplan as well as its power-pin distribution into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability by up to 7 times with an average performance overhead of 4.0%.

Voltage emergency prediction: Using signatures to reduce operating margins

“…Issue-rate staggering. Pipeline muffling [20,23] and a floor-plan aware di/dt controller [17] both stagger issue rates to combat cycle-to-cycle high-frequency noise within individual microarchitectural units. In contrast, this paper considers inductive noise in the mid-frequency (10-100MHz) range that impacts the entire chip over periods of tens of cycles.…”

Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling

“…However, in cases when the current threshold is exceeded, a dynamic di/dt control mechanism at the microarchitecture level is still needed to handle the potential noise emergency in addition to our noise tolerable floorplan. It is achieved by dynamically throttling a processor's activity [10,15,23] at the potential cost of performance degradation. By coupling noise-aware floorplanning with dynamic di/dt control, we can guarantee that our floorplan for the average case is more noise tolerant.…”

“…Recently, researchers [10,15] advocated incorporating dynamic di/dt control at the microarchitectural level to avoid excessive voltage ringing in the power supply. By including current calculation into microarchitectural simulations, these techniques analyzed benchmark behavior and used it to guide the dynamic di/dt control.…”

“…In contrast, we address this issue early in the architectural planning phase, thereby reducing decap requirements and design complexity. By floorplanning for the average case using the techniques we propose with dynamic di/dt control schemes [15] to account for the worst case, we can ensure a design that is far more resistant to inductive noise than a purely wirelength driven floorplan.…”

Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors

“…Many previous works have focused on detailed modeling of the power supply network, while ignoring the actual currents and switching activities generated from architectural profiling [12], [13], [3], [27], [26]. On the other hand, some recent works focus on microarchitectural profiling but use an oversimplified power grid model to estimate the PSN of the system [19], [18], [11].…”