A floorplan-aware high-level synthesis technique with delay-variation tolerance

Kawamura, Kazushi; Hagio, Yuta; Shi, Youhua; Togawa, Nozomu

doi:10.1109/edssc.2015.7285065

Cited by 2 publications

(1 citation statement)

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“…Several static-delay-variation aware high-level synthesis algorithms are proposed [2,3]. But most of them assume only static delay variation due to process variation and cannot be applied to dynamic delay variation.…”

Section: Introductionmentioning

confidence: 99%

Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

Igawa

Yanagisawa

Togawa

2016

IEICE Electron. Express

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Multi-scenario high-level synthesis for distributed register/controller architecture has been proposed targeting static delay variation. In this paper, we extend it and propose a floorplan-driven high-level synthesis algorithm which can be applied to dynamic delay variation by effectively using an error prediction technique, where pre-error registers are introduced to local registers in every circuit block. Experimental results show that the proposed algorithm using two and three scenarios on an FPGA chip reduces the average number of required control steps by 17.6% and 25.5% on average compared to worst-case high-level synthesis at the expense of increasing lookup-tables and flip-flops. Moreover, we implement a multiscenario elliptic-wave-filter (EWF) circuit with three scenarios synthesized by our proposed algorithm onto an FPGA chip and run it under the environment with varying supply voltages which causes dynamic delay variation. The FPGA implementation experiments also demonstrate that the EWF circuit effectively runs on the real FPGA chip. As far as we know, this is the world-first experiment where a multi-scenario circuit runs under real dynamic delay variation environment.

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Section: Introductionmentioning

confidence: 99%