A formal concurrency model based architecture description language for synthesis of software development tools

Qin, Wei; Rajagopalan, S.; Malik, Sharad

doi:10.1145/997163.997171

Cited by 31 publications

(12 citation statements)

References 11 publications

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“…We have modeled an Alpha 21264 like superscalar processor in the SimpleScalar architectural simulation framework [2]. We specify the ISA in MESCAL Architecture Description Language (MADL) [9]. This includes static properties of the instructions such as operation semantics, assembly syntax, and binary encodings.…”

Section: Experimental Evaluationmentioning

confidence: 99%

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Generating test programs to cover pipeline interactions

Dang

Roychoudhury

Mitra

et al. 2009

Proceedings of the 46th Annual Design Automation Conference

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Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural specification driven methodology for systematic test-suite generation. Our primary contribution is an automated test-suite generation methodology that covers all possible processor pipeline interactions. To accomplish this automation, we (1) develop a fully formal processor model based on communicating extended finite state machines, and (2) traverse the processor model for on-the-fly generation of short test programs covering all reachable states and transitions. Our test generation method achieves several orders of magnitude reduction in test-suite size compared to the previously proposed formal approaches for test generation, leading to drastic reduction in validation effort.

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Section: Experimental Evaluationmentioning

confidence: 99%

“…Instead, we develop a formal processor model based on communicating extended finite state machines. Our model is an extension of the Operation State Machine (OSM) model [8] proposed in the context of MESCAL Architecture Description Language (MADL) [9].…”

Section: Introductionmentioning

confidence: 99%

Generating test programs to cover pipeline interactions

Dang

Roychoudhury

Mitra

et al. 2009

Proceedings of the 46th Annual Design Automation Conference

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“…The OSM model was initially proposed to model processors [11]. It is based on the observation that the execution progress of an operation, i.e.…”

Section: Osm Basicsmentioning

confidence: 99%

“…First, we propose a novel modeling methodology of on-chip communication architecture based on a formal concurrency model, the Operation State Machine (OSM) [11]. Previously this model has been applied successfully in modeling microarchitectures of processors.…”

Section: Introductionmentioning

confidence: 99%

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

Zhu

Qin

Malik

2006

IEEE Trans. VLSI Syst.

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In multiprocessor based SoCs, optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation archi-tectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time; at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation level concurrency maps to the microarchitectural level concurrency. This paper presents a mod-eling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication subsystem through a rigorous modeling approach based on a formal concurrency model, the Operation State Machine (OSM). We first introduce the basic notions and concepts of OSM and show by example how this model can be used to represent the inherent concurrency in the architecture and microarchitecture of processors. Then we demonstrate the applicability of OSM in modeling on-chip communication architectures (OCAs) by walking though a router based packet switching network example and a bus example. Due to the fact that the OSM model is naturally suited to handle the operation and microarchi-tecture level concurrencies of OCAs as well, our OSM-based mod-eling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multi-PE SoC prototypes. To demonstrate the flexibility of this methodology, we choose two distinct system configurations with different types of OCA: a 4x4 mesh network of 16 PEs, and a cluster of 4 PEs connected by a bus. We show that by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design. In addition to improving design quality, this methodology also results in significantly shortened design-time.

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“…Recently, various Architecture Description Languages (ADLs) have emerged. ADLs describe the instruction-set architecture (ISA) as well as the microarchitecture of a given platform [18,4]. Researchers have studied the retargetability issues in the context of ADL-driven compilation [15,18], simulation [14], hardware synthesis [16] as well as functional validation [12].…”

Section: Introductionmentioning

confidence: 99%

A Retargetable Software Timing Analyzer Using Architecture Description Language

Roychoudhury

Mitra

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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Worst Case Execution Time (WCET) is an essential input for performance and schedulability analysis of real-time systems. Static WCET analysis requires program path analysis and microarchitecture modeling. Despite almost two decades of research, WCET analysis has not enjoyed wide acceptance in industry. This is in part due to the difficulty in microarchitecture modeling of modern processors. Given the large number of embedded processors available in the market, retargetability of the WCET analysis framework is a serious issue. In this paper, we address it using Architecture Description Language (ADL). Starting with the ADL of a target processor, the proposed framework automatically generates graph-based execution models to capture timing effects of instructions in the pipeline. This pipeline model coupled with parameterized models of cache and branch prediction lead to a WCET framework that is safe, accurate and retargetable.

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A formal concurrency model based architecture description language for synthesis of software development tools

Cited by 31 publications

References 11 publications

Generating test programs to cover pipeline interactions

Generating test programs to cover pipeline interactions

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

A Retargetable Software Timing Analyzer Using Architecture Description Language

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