A formal method for hardware IP design and integration under I/O and timing constraints

Abstract

IP integration, which is one of the most important SoC design steps, requires taking into account communication and timing constraints. In that context, design and reuse can be improved using IP cores described at a high abstraction level. In this paper, we present an IP design approach that relies on three main phases: (1) constraint modeling, (2) IP constraint analysis steps for feasibility checking, and (3) synthesis. We propose a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration. Based on a generic architecture of components, the method we propose provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach with a DCT core design case study.

Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis

“…7 describes a general synchronization example, using the Input Output Constraints Graph (IOCG) presented in [5]. The BDM is composed of N (N input processes) input ports and M output ports (N output processes).…”

“…More details can be found in [5]. By using explicit synchronization relations, the designer can specify any timing execution order between read and write operations.…”

“…For each timing behavior of each BDM component, an I/O trace file has been automatically generated during the functional SystemC simulation. These traces have next been used as I/ O timing constraints for high level synthesis of the components [5]. Synthesis results have been obtained by using the HLS tool GAUT [7,8] with a 10ns clock period constraint.…”

A multiple neighborhood search for dynamic memory allocation in embedded systems

“…This is possible thanks to the continuous advances in nano-technology, which enables us the use of miniaturized and ever increasing complexity chips. In order to take on the challenge of such a complexity growth, new design methodologies have been proposed on the basis of high-level abstraction (Coussy et al 2006): designers are no longer required to take care of architectural details and only have to focus on high-level specifications (Dorf 2010).…”

A mathematical model and a metaheuristic approach for a memory allocation problem

“…Soto · A. Rossi · M. Sevaux ( ) Lab-STICC, CNRS, UMR 3192 Centre de Recherche, Université de Bretagne-Sud, BP 92116, 56321 Lorient Cedex, France e-mail: marc.sevaux@univ-ubs.fr For a long time, electronic chips used to be designed manually by experts who mastered a given technology, and were able to control the complexity of the whole product. Such a line of design is no longer possible, and computer-aided design softwares like Gaut (Coussy et al 2006) have been developed to generate chips from their specifications. While the design process is significantly faster with these types of software, the generated layouts are considered to be poor on power consumption and surface compared to human expert designed circuits.…”