A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Abstract

A formal semantic analysis for Verilog-HDL and VHDL is provided in order to give the simulation model especially focusing on signal scheduling and timing control mechanism. Our semantics is faithful to LRM and is expected to become a coherent first step for a future semantic interoperability analysis on multisemantic-domain such as Verilog-AMS and VHDL-AMS. By ignoring the differences of the two simulation cycles, we can use the common semantic functions and the common simulation cycle.

The abstract state machines method for modular design and analysis of programming languages

“…In [41,42] we defined an asynchronous ground model ASM for the, at the time new, IEEE standard [111] of the hardware design language VHDL, including the characteristic signal behavior and time model (with pulse rejection limits and the various wait and signal assignment statements involved in the subtle issues related to postponed processes). These ASM models were reused a) in W. Müller's PhD thesis [137] for defining the semantics of a pictorial extension PHDL of VHDL'93, b) by a group of Toshiba engineers for an extension to analog VHDL and Verilog [155,156,152,154,153], and c) for an adaptation to SystemC [133,134] and to SpecC [132]. Montages 24 in logic programming languages mentioned above [148,46,47,17] and in the Chemical Abstract Machine and the π-calculus [91].…”

The formal execution semantics of SpecC

“…The latter covered VHDL'93 and was extended for VHDL-AMS in [12]. Other applications investigated VHDL-Verilog interoperability [ 11]. Most recently, Sys-temC simulation semantics have been published in [ 1 O] which is oriented towards the VHDL'93 definitions in [2].…”

Towards a theory of bisimulation for a fragment of Verilog

“…Following his work, many attempts to give a formal semantics of Verilog are in progress. These work use a variety of techniques including labelled transitions system(Xu and Gerardo) [7], abstracted state machine (Hisashi Sasaki) [4], reduction semantics (Fiskio-Lasseter and Amr Sabry) [5]. These semantics provide excellent documentation of the simulation semantics of the language but do not seem to be particularly suited for proofs about large programs.…”