A four-quadrant analog multiplier using DTMOS for low power applications

Özer, Emre; Başak, Muhammed Emin; Kaçar, Fırat

doi:10.1080/00207217.2022.2062795

Cited by 5 publications

(1 citation statement)

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“…In order to reduce the power consumption of analog integrated circuits, operations with lower supply voltages can be provided by DTMOS technology [33][34][35][36][37]. To obtain a DTMOS transistor, the body and gate terminals of the MOSFET are short-circuited as shown in Figure 6.…”

Section: Simulation Resultsmentioning

confidence: 99%

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

Vahbeh,

Özer,

Kaçar

2024

Electronics

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In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

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