A Four Quadrant S2I Switched-Current Multiplier

Abstract

Abstract-The analysis, design, and implementation of a twostep current-sampling switched-current (S 2 I) multiplier is presented. The S 2 I technique has been employed to compensate analog errors due to charge injection as well as those arising from the finite output impedance. A thorough circuit analysis investigating the offset sources of the S 2 I cell and of the multiplier's nonlinearities sets up the platform to effectively design the multiplier and to avoid the use of feedback, or cascode techniques, to deal with channel modulation effects. The multiplier has been implemented using a 2-m n- A complete set of detailed experimental results is provided in the paper.

A current-mode analog multiplier/divider based on CCCDTA

“…Realizations of the current-mode multipliers and dividers can be separated into two main techniques, which are continuous-time signal and sampled-time signal based on switched-capacitor or switched-current technique [9,10]. The latter method needs to inevitably employ clock signal to activate the circuit.…”