A four-terabit packet switch supporting long round-trip times

Audigier, François; Minkenberg, Cyriel; Luijten, Ronald P.; Gusat, Mitch; Iliadis, Ilias

doi:10.1109/mm.2003.1179894

Cited by 56 publications

(26 citation statements)

References 13 publications

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“…The crossbar-based fabric switch is the dominant architecture for today's high-performance packet switches [1] [2]. The fabric of a crossbar-based packet switch can be either unbuffered [1] or internally buffered [2].…”

Section: Introductionmentioning

confidence: 99%

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Buffered Crossbar Fabrics Based on Networks on Chip

Mhamdi

Goossens

Senin

2010

2010 8th Annual Communication Networks and Services Research Conference

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Abstract-Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratically with the port count. Additionally, similar to traditional crossbars, point-to-point switching mandates the use of long wires to connect inputs to outputs, resulting in non-negligible delays. In this paper, we propose a CICQ switching architecture where the buffered crossbar fabric is designed using a Network on Chip (NoC). Instead of a dedicated buffer for every pair of input-output ports, we use on-chip routers, one for each crosspoint. Our design offers several advantages when compared to traditional CICQs: 1) speedup, because the fabric can operate faster due to the small size of the NoC routers, their distributed arbitration and the short wires connecting them. This is in contrast to single-hop crossbars that use long wires and centralized arbitration. 2) Load balancing, because flows from different input-output port pairs share the same router buffers, contrary to the internal buffers of traditional CICQs that are dedicated to a single input-output pair. 3) Path diversity, allowing traffic from an input port to follow different paths to its destination output port. This results in further load balancing, especially for non-uniform traffic, and provides better fault tolerance in the presence of interconnect failures. We analyzed the performance of our architecture by simulation and presented its performance under wide traffic conditions and switch sizes. We prototyped, in CMOS technology, a 32×32 NoC-based crossbar switch. The implementation results suggest that we can clock the switch at a frequency of 413 MHZ, reaching an aggregate throughput in excess of 10 10 ATM cells per second.

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Section: Introductionmentioning

confidence: 99%

“…The fabric of a crossbar-based packet switch can be either unbuffered [1] or internally buffered [2]. The similarity between these two variants lies in the quadratic growth of their cost with the number of switch ports.…”

Section: Introductionmentioning

confidence: 99%

Buffered Crossbar Fabrics Based on Networks on Chip

Mhamdi

Goossens

Senin

2010

2010 8th Annual Communication Networks and Services Research Conference

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“…In this framework, [10] and [11] propose solutions for supporting multiple priorities in BX switches. The former uses a single memory at each crosspoint, shared between multiple queues, thus causing buffer-hogging.…”

Section: Introductionmentioning

confidence: 99%

Size-based flow scheduling in a CICQ switch

Divakaran

Anhalt

Altman

et al. 2010

2010 International Conference on High Performance Switching and Routing

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In the context of flow-aware networking, size-based (SB) scheduling policies have been shown to improve response times of small flows, without degrading the performance of large flows. But these differentiating policies are designed for Output-queued (OQ) switch architecture, which is known to have scalability issues. On the other hand, the buffered-crossbar (BX) switch architecture is currently being pursued as a potential next-generation scalable switch architecture. This work looks into the problem of performing SB scheduling in BX switches. In particular, the design goals, with respect to each output port, are (i) to transmit high-priority packet(s) as long as there is at least one present, and (ii) to respect the FIFO order among high-priority packets. In this direction, we propose a CICQ switches using a single PIFO queue at each crosspoint to schedule packets according to the priority assigned. pCICQ-1 switch uses a simple design to guarantee that packet-priorities are respected once they are in the crosspoint queues. But it does not maintain the FIFO order of high-priority packets, besides letting a bounded number low-priority packets to depart through an output, when there are one or more high-priority packets for the same output. To solve this, we propose an enhancement in pCICQ-2 switch, that uses a sequence controller to respect packet-priorities as well as arrival order for high-priority packets.Key-words: scheduling, switch, piority, CICQ Ordonnancement de flux basé sur la taille dans un switch CICQ Résumé : Dans un contexte du traitement par flux, il aété montré que les politiques d'ordonnancement basées sur la taille (size-based (SB)) améliorent le temps de réponse des petits flux, sans dégrader la performance des autres flux. Ces politiques de différenciation sont conues pour des architectures de switch ayant des files d'attente aux ports de sortie (output queued (OQ)), et dont on sait qu'ils sont limités dans le passageà l'échelle. Comme solutionà ce problème de passageà l'échelle, l'architecture de switch avec une matrice de commutationéquipée de buffers aux points d'intersection (buffered crossbar (BX)) est actuellement vue comme pouvantêtre l'architecture des switches de demain. Ce travail examine le problème de réaliser un ordonnancement basé sur la taille dans de tels switches ayant une matrice de commutation avec des buffers. Plus particulièrement, les objectifs au niveau de chaque port de sortie sont (i) de toujours transmettre les paquets prioritaires en premier, et (ii) de respecter l'ordre FIFO entre les paquets prioritaires. Dans ce but, nous proposons un switch CICQ qui utilise une file d'attente PIFOà chaque point d'intersection, afin d'ordonnancer les paquets en fonction de leur priorité. Le switch pCICQ-1 utilise un concept simple pour garantir le respect des priorités des paquets une fois qu'ils ont atteint les files d'attentes aux points d'intersection. Parcontre, il ne maintient pas l'ordre FIFO entre les paquets prioritaires et peut admettre un nombre limité de paqu...

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“…However, the predominant creditbased flow control [10] used in CICQ may suffer from the effect of large fabric-internal latency [1][13] [14]. It makes the internal buffer size increase considerably with the growing distance between the line cards and the switch core in the multi-rack and multi-terabit switches.…”

Section: Introductionmentioning

confidence: 99%

Practical Algorithms of Bandwidth Regulation for Rate-Based Switching

Wang¹,

He²,

Zhao³

et al. 2007

IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference

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Abstract-A rate-based switch fabric called smoothed buffer crossbar has been proposed in our recent work. It can provide 100% rate-guaranteed service with only a two-cell buffer at each crosspoint, and can also support best-effort service with an additional bandwidth regulator. However, the widely used maxflow model for bandwidth regulation is neither scalable nor of 100% throughput. In order to evaluate the performance of bandwidth regulator, we first introduce the 100% ideal throughput measurement in this paper. Then we prove that the total arrival average (TAA) algorithm has got this property, which does not happen in the max-flow allocation. Then an O(N) algorithm called proportion scaling allocation (PSA) is presented. Simulations reveal that PSA can deliver nearly 100% throughput even in a frequently changing traffic pattern. As a comparison, both theoretical and experimental evidences are given to show the inefficiency of the max-flow model. Index Terms-switch fabric, rate-based switching, bandwidth regulation, scheduling.

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A four-terabit packet switch supporting long round-trip times

Cited by 56 publications

References 13 publications

Buffered Crossbar Fabrics Based on Networks on Chip

Buffered Crossbar Fabrics Based on Networks on Chip

Size-based flow scheduling in a CICQ switch

Practical Algorithms of Bandwidth Regulation for Rate-Based Switching

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