2007
DOI: 10.1109/tuffc.2007.354
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A fractional filter-based beamformer architecture using postfiltering approach to minimize hardware complexity

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Cited by 14 publications
(17 citation statements)
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“…2) Multi-Beamforming Method Based on a Shared FIFO Block: In the PUS-SOC, an MBF method based on a shared FIFO block supporting single-, dual-, and quad-beamforming is implemented in a dynamic receive beamforming architecture based on post-fractional filtering [15], [21]. The MBF method can produce multiple scanlines simultaneously without reducing the beamforming frequency, unlike the conventional time-sharing MBF method [22].…”
Section: ) Pseudo-dynamic Delay Calculationmentioning
confidence: 99%
See 1 more Smart Citation
“…2) Multi-Beamforming Method Based on a Shared FIFO Block: In the PUS-SOC, an MBF method based on a shared FIFO block supporting single-, dual-, and quad-beamforming is implemented in a dynamic receive beamforming architecture based on post-fractional filtering [15], [21]. The MBF method can produce multiple scanlines simultaneously without reducing the beamforming frequency, unlike the conventional time-sharing MBF method [22].…”
Section: ) Pseudo-dynamic Delay Calculationmentioning
confidence: 99%
“…The RF data are fed into the dynamic receive beamformer (RxBF) module through the low-voltage differential signaling block (LVDS) in the PUS-SOC and sequentially stored in RF memory. The RxBF module provides up to 4 simultaneous scanlines; the module is based on a post-fractional delay filtering architecture composed of a shared first-in-first-out (FIFO) block, a selective summation block (SSB), and a fractional delay filtering block (FDF) [15]. The beamformed results are sent to the mid-processor, which performs direct current rejection filtering (DCR), data decimation, scanline accumulation (SLA), time-gain compensation (TGC), digital quadrature demodulation (DQD), and baseband code compression (BCC).…”
mentioning
confidence: 99%
“…On the other hand, in IBF-POST, block data are selected by coarse delay and accumulated to a block buffer memory according to fine delay (i.e., D=0, D=0.25, D=0.5 and D=0.75 where D is fine delay). Consequently, accumulated block data are filtered with a polyphase filter [11].…”
Section: ) Ibf-pre Vs Prbf-postmentioning
confidence: 99%
“…2 shows the block diagram of the developed USI system which consists of the ASIC-US, Virtex-4 FPGA, DSP (TMS320C6416TGLZ) and Samsung mobile CPU (S3C6410XH). The ASIC-US performs transmit beamforming, low-voltage differential signaling (LVDS) receiver block, 32-channel receive beamforming, and mid/back-end processing with hardware-efficient and performance enhancing architecture and algorithms, e.g., post-fractional filter based receive beamforming architecture, time-sharing bilinear receive focusing delay interpolation, extended aperture, multi-access register based multi-beamforming, dynamic quadrature demodulation, and frequency compounding algorithm [9][10][11][12][13]. FPGA was used for interface between the ASIC-US and DSP, and real-time control for the USI system, e.g., sequence generation and CPU interface.…”
Section: Introductionmentioning
confidence: 99%