A framework for early and systematic evaluation of design rules

Abstract

Abstract-Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusionrounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65nm process, which serves as a validation for our approach.

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

“…In this paper, we extend our work presented in [19]. To the best of our knowledge, this work proposes the first framework to systematically and qualitatively explore areamanufacturability-variability tradeoffs in design rules.…”

A methodology for the early exploration of design rules for multiple-patterning technologies

“…Once the front-end layers are created and contact locations are determined, we generate a number of possible wiring solutions for each net (unlike [9], where the wiring of each net is estimated with a single solution). For each cell layout, the generation of wiring solutions undergoes the following steps.…”

“…For our baseline experiment, we use a cell-height of 10 M2-tracks, 1D polysilicon (poly), and local interconnect (LI) to perform gate-to-gate connections 9 . Our methodology, layout/congestion estimation followed by the machine-learning model, is run to predict the presence of DP conflicts in M1 layouts.…”

“…For this estimation, the design-rules exploration framework of [8] was used. The framework employs layouttopology generation methods that were shown to be fast and accurate [9], which makes it well suited for our approach. For more details, the reader is referred to [9].…”

“…The framework employs layouttopology generation methods that were shown to be fast and accurate [9], which makes it well suited for our approach. For more details, the reader is referred to [9]. The next step is to estimate the layout for back-end layers used within the cells (i.e., M1 in our experiments).…”