A framework for high‐speed parallel‐prefix adder performance evaluation and comparison

Abstract

Summary A new framework is proposed for the evaluation and comparison of high‐speed parallel‐prefix adders. The framework specifies input registers and latches and requires sum feedback for single cycle pipelined operation. Test pattern generation is also specified. A newly revised energy‐efficient 64‐bit carry select adder with distributed mixed valence logic to help reduce fan‐out and wire load is presented. Footless pulsed‐precharge domino and compound domino circuits, and smaller transistors help to reduce area and power. Detailed simulations with 65 nm CMOS models are compared with other parallel‐prefix adders that have been instantiated for comparison. Within this framework, energy reductions of 40% are obtained for the new adder versus two leading Kogge‐Stone designs, and 25% versus a new constant delay logic Sklansky style design, at similar cycle times. Copyright © 2014 John Wiley & Sons, Ltd.

A novel generic modulo‐2 graph with full set taxonomical conversion to parallel prefix adders

“…11 Also, different algorithms id applied on PPAs for designing the low power and highspeed adder. 12,13 Generally, there are two ways to design the adders. These approaches are manually using custom design and automatic method using synthesis tools.…”

“…In addition, design of hybrid PPAs is proposed as a one way for increasing the performance of PPAs, 8–10 and these adders can be used as a fast adder in parallel decimal multipliers 11 . Also, different algorithms id applied on PPAs for designing the low power and high‐speed adder 12,13 …”