2005
DOI: 10.1145/1080334.1080336
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A framework for systematic validation and debugging of pipeline simulators

Abstract: Microprocessor pipeline simulation at the system level is an extremely important activity in the architecture exploration process. In this article, we address the problem of validating and debugging a pipeline simulator from the specific perspective of instruction scheduling. We propose a general framework for a systematic validation process and show that the assumptions made are justified for most standard pipeline models. The framework does not need any formal specification of the pipeline logic and hence ca… Show more

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