A framework of architectural synthesis for dynamically reconfigurable FPGAs

Abstract

Reconfiguration latency is an important factor which impacts the system performance in the reconfigurable computing design. In this paper, a framework is proposed that presents a novel approach for an optimal implementation of algorithms on FPGA based reconfigurable system. The method optimizes the temporal partitioning by performing a similar-rate-computing-based architectural synthesis. It gives the possibility to merge the related partitions during the implementation of a target architecture by the architectural synthesis based on reusing of the common task. Our approach proposes a final solution based on the computation of the mutual similar rate (M.S.R.) for a RTR implementation with a synthesis option. The proposed approach attempts to reduce the number of the temporal partitions for minimizing the overall execution time. An example is presented to illustrate this novel approach. With the architectural synthesis, the number of partition was decreased. The results demonstrate that are capable and efficient for an optimized implementation in the reconfigurable design.

Optimized and robust implementation of mobile networks confidentiality and integrity functions

“…Firstly, we combined the internal blocks of the original F8 and F9 functions to reduce the required area for hardware implementation [4,5]. The adopted technique is based on the reuse of common blocks for original functions [6,7], principally KASUMI algorithm [8][9][10]. Secondly, we simplified the implementation of the internal functions (FL, FO, and FI) of the KASUMI block cipher (the core of standard F8 and F9 functions) to increase the encryption throughput.…”

FPGA implementation of an optimized A5/3 encryption algorithm

“…In the second part, we proposed an optimized A5/3 algorithm based on the proposed optimized KASUMI to ensure the same functionalities (produce 228-bits each 4.615 ms [10]) of the original A5/3 algorithm made up five components of the original KASUMI block cipher [11,12]. In this study, we used the synthesis architectural technique corresponding to the reuse by factorization of logic/arithmetic operators [13]. This technique allows the connection between different internal components which are managed by a tailored control unit based on Moore's Finite State Machine (FSM).…”