A framework to quantify FPGA design hardness against radiation-induced single event effects

Abstract

This paper describes current ongoing research pertaining to the analysis of design radiation hardness for circuits implemented in Field-Programmable Gate Array (FPGA) devices. Radiation induces single event effects in FPGAs that can cause erroneous operation by upsetting data bits or changing logic behavior. Design-level techniques can help mitigate these upsets to some degree; however, there is currently no method available to quantify the benefit of these techniques after they are incorporated into a design. This research strives to develop a framework to analyze FPGA netlists and score a design in terms of upset hardness. Additionally, this framework will develop a method to determine the most upset-susceptible locations in design netlists and help identify areas of circuits that would most benefit from additional design mitigation.