A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System

Dasygenis, Minas; Mitroglou, K.; Soudris, Dimitrios; Thanailakis, A.

doi:10.1109/tcsi.2007.913608

Cited by 10 publications

(32 citation statements)

References 18 publications

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“…It was suitable for small-word-length applications and performed scaling directly on the residue digits rather than relying on residue-tobinary conversion. From the implementation point of view, scaling algorithms are implemented either in LUT (look up table) based approaches [7], [15], [16], [17], [21], [22], [23], or adder-based approaches [5]. Generally, all the LUT-based designs in the literature are subject to poor pipeline-ability and high hardware complexity when the number of moduli increases.…”

Section: Related Workmentioning

confidence: 99%

RNS Scaling Algorithm for a New Moduli Set {2^(2n+1) +1, 2^(2n+1), 2^(2n+1)-1}

Mustapha¹,

Bankas²

2017

IJCA

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Scaling is one of the difficult operations in Residue Number System (RNS) and also one of the most important units and a necessary operation used to avoid overflow in RNS based systems. In this paper, a scaling algorithm for a new moduli set {2 2n+1 +1, 2 2n+1 , 2 2n+1 -1} using the Chinese Remainder Theorem (CRT) is presented. In the design of digital systems, the goal of designers is to increase performance and decrease the amount of hardware resources. In order to achieve this, a new moduli sets is proposed to obtain a larger dynamic range and less complex hardware architecture. The CRT is further simplified for the selected moduli set to reduce the hardware complexity of the scaling algorithm. The scaling algorithm does not introduce any scaling errors and thus is efficient. When compared with the state of the art scaling algorithm using the Unit-Gate model, the results show that, the proposed scaling algorithm outperforms the state of the art scaling algorithm in terms of dynamic range (DR), area consumption, and delay by 98%, 18.4% and 21.7% respectively. General TermsModuli Set, Scaling Algorithm, Residue Number System, Chinese Remainder Theorem.

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Section: Related Workmentioning

confidence: 99%

RNS Scaling Algorithm for a New Moduli Set {2^(2n+1) +1, 2^(2n+1), 2^(2n+1)-1}

Mustapha¹,

Bankas²

2017

IJCA

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“…The RNS number (12,25,2) can be converted into its equivalent weighted number by doing the following steps: 1) Binary representation of residues (12)- (14): (61):…”

Section: Numerical Examplementioning

confidence: 99%

“…However, the difficulties which have existed in implementation of non-modular RNS operations, as well as the overhead incurred by forward and reverse converters, were preventing the usage of RNS in general-purpose processors. But, the recent achievements to perform difficult RNS operations such as sign detection [10], magnitude comparison [11] and scaling [12] promote the increase in applicability of RNS in general-purpose computing systems. The most imperative issue to design efficient RNS systems is appropriate selection of moduli set since the performance of residue arithmetic channels as well as the complexity of forward and reverse converters depends mainly on the form and the number of moduli [13].…”

Section: Introductionmentioning

confidence: 99%

A General Reverse Converter Architecture with Low Complexity and High Performance

Navi

Esmaeildoust

Molahosseini

2011

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a general architecture for designing efficient reverse converters based on the moduli set {2 α , 2 2β+1 -1, 2 β -1}, where β ≺ α 2β, by using a parallel implementation of mixed-radix conversion (MRC) algorithm. The moduli set {2 α , 2 2β+1 -1, 2 β -1} is free from modulo (2 k +1)-type which can result in an efficient arithmetic unit for residue number system (RNS). The values of α and β can be selected to provide the required dynamic range (DR) and also to adjust the desired equilibrium between moduli bit-width. The simple multiplicative inverses of the proposed moduli set and also using novel techniques to simplify conversion equations lead to a low-complexity and high-performance general reverse converter architecture that can be used to support different DRs. Moreover, due to the current importance of the 5n-bit DR moduli sets, we also introduced the moduli set {2 2n , 2 2n+1 -1, 2 n -1} which is a special case of the general set {2 α , 2 2β+1 -1, 2 β -1}, where α=2n and β=n. The converter for this special set is derived from the presented general architecture with higher speed than the fastest state-of-the-art reverse converter which has been designed for the 5n-bit DR moduli set {2 2n , 2 2n+1 -1, 2 n -1}. Furthermore, theoretical and FPGA implementation results show that the proposed reverse converter for moduli set {2 2n , 2 2n+1 -1, 2 n -1} results in considerable improvement in conversion delay with less hardware requirements compared to other works with similar DR. key words: residue arithmetic, reverse converter, residue number system (RNS), VLSI architecture

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“…The first and only full adder (FA) based exact scaling algorithm that operates directly on the residue digits was proposed by Dasygenis et al [Das08]. It uses the axiom,…”

Section: Full-adder Based Exact Scaling [Das08]mentioning

confidence: 99%

“…In other words, the proposed scaling algorithm has successfully circumvented the complexity of RNS scaling problem for {2 1, 2 , 2 1} For consistency, the same method of evaluation as [Das08] is adopted so that the hardware area and time complexity of the contending designs can be excerpted directly from As the use of RNS scaler is to ensure that the computed result represents the real value instead of its residue modulo M, it is fairer to compare different RNS scalers based on the same dynamic range. As this is not always possible due to the odd values of moduli selected by [Das08], the value of n for the proposed design has been selected such that its dynamic range is at least several time larger than the dynamic range of other designs so that the comparison is always in favor of the contenders. Table 3.5 and Table 3.6 show the comparisons of the transistor counts and the delay, respectively, of six different RNS scaling architectures for four different dynamic ranges.…”

Section: Evaluation and Comparisonmentioning

confidence: 99%

VLSI efficient RNS scalers and arbitrary modulus residue generators

Low¹

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Carry propagation has been identified as the main timing bottleneck of the datapath elements of application-specific digital signal processors in the accustomed positional number system. Residue Number System (RNS), being a non-weighted number system, emerges as a good remedy to this problem. RNS gains phenomenal successes in speeding up the datapath of digital signal processing applications dominated by additions/subtractions and multiplications, such as digital filters, convolution, channelizers, equalizers, discrete transforms, etc. Despite xii

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A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System

Cited by 10 publications

References 18 publications

RNS Scaling Algorithm for a New Moduli Set {2^(2n+1) +1, 2^(2n+1), 2^(2n+1)-1}

RNS Scaling Algorithm for a New Moduli Set {2^(2n+1) +1, 2^(2n+1), 2^(2n+1)-1}

A General Reverse Converter Architecture with Low Complexity and High Performance

VLSI efficient RNS scalers and arbitrary modulus residue generators

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