A full-scale complementary dynamic comparator

Abstract

This paper presents a dynamic comparator that achieves precise comparison across the entire full-scale range. The comparator, an essential component module in analog-to-digital converters (ADCs), is influenced by its input signal range, speed, and offset voltage, all of which impact the ADC’s performance. In the proposed comparator, a pre-amplification stage using PMOS as the input is incorporated alongside the comparator utilizing NMOS as the input, creating a complementary structure. This design ensures that at least one pre-amplification stage operates effectively, thereby maintaining the accuracy of the comparator as the input signal varies across the entire full-scale voltage range (0 to VDD). Through sound circuit design, the proposed comparator effectively avoids introducing additional distortion and noise. The performance of the comparator is verified under the 180 nm process. The comparator achieves accurate comparison across the entire full-scale range, with a standard deviation σ of the input offset voltage of 6 mV, noise of 450 uV, and a layout area of 467.36 um2. Simulation results demonstrate that the comparator exhibits excellent performance, providing stability assurance for the ADC and extending the ADC’s input signal range.