In this work we address the problem of estimating the mechanical stress and the related risk of crystal defect generation in a complex device process. The validity of numerical calculations of the mechanical stress developed in the device process flow is assessed by comparing the simulation results with the electrical measurements of test structures designed to monitor the dislocations formation and of other silicon strain sensitive structures. The results show that based upon numerical calculations it is possible to define mechanical stress criteria for preventing defect generation. By using this sort of criteria, potentially dangerous process variations can be easily identified. This method is quite general and can be applied to any device process flow. On the other hand, by comparing the electrical results of structures prone to defect generation and of stress-sensitive transistors with a non-critical geometry for defect generation, it is shown that after defect nucleation the elastic stress in non-critical structures and the defect-related failure fraction in critical structures may evolve into opposite directions. Therefore, suitable stress criteria are needed at all the levels in the process flow where crystal damage may cause defect nucleation. In this study it is also pointed out that a high temperature stress release annealing can be beneficial for stress reduction and defect prevention, but its position in the process flow is critical.