A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms

Abstract

The transistor celebrated its 75 th birthday in 2022. The continued scaling of the transistor defined by Moore's Law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms.

Training Deep Boltzmann Networks with Sparse Ising Machines

“…In this approach, a graph comprised of N p-bits is able to perform a full sweep in a single clock cycle (T clk ). We refer to this architecture as the pseudo-asynchronous Gibbs sampling [10]. The key advantage of this approach is that the p-computer becomes faster as the graph size grows as shown in Fig.…”

“…Despite our FPGA-specific design in this paper, much of our results are applicable to scaled p-computers as well as other Ising machines based on many different physical realizations [1]. Our broader goal is to help stimulate the development of physics-inspired probabilistic hardware [10,11] which can lead to energyefficient systems to reduce the rapidly growing costs of conventional deep learning based on graphics and tensor processing units (GPU/TPU) [12].…”

Neural networks three ways: unlocking novel computing schemes using magnetic tunnel junction stochasticity

“…13 FPGA-and ASIC-based coupling of p-bit devices described in the previous section has proven to be extremely versatile for a wide range of computational problems. 14 However, it is tempting to ask whether we can connect these devices with direct electrical signals rather than digital control, the latter of which often comes with non-negligible area and energy consumption overheads.…”

The stochastic ferroelectric field-effect transistors-based probabilistic-bits: from device physics analysis to invertible logic applications

“…Many of the hard computational problems [1][2][3] require new architectures to be efficiently addressed, as the conventional computing architectures are often with high-energy consumption. Probabilistic computing (PC) [4][5][6][7] receives increasing attention as a solution to both accelerate the solving process and be energetically efficient. The fundamental component in the PC circuitry is the probabilistic-bit (p-bit), 4) which could generate a continuous random digital bitstream with tunable probability.…”