A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

Abstract

A fully integrated 100 kHz X-ray charge coupled device (CCD) readout application specific integrated circuit (ASIC) employing delta sigma (ΔΣ) digitization is presented. To achieve high linearity with small chip size and low power consumption, the correlated double sampling (CDS) is realized by the ΣΔADC instead of the analog front end (AFE) as in conventional CCD readout circuits. Besides, the proposed decimation filter features simple structure and eases the integration. The chip is fabricated in 0.35 µm CMOS technology and the measured integral nonlinearity (INL) throughout the input dynamic range of ASIC is 0.055% with 35.1 ± 0.3 µV input referred noise. A CCD detection system is built and tested with the sensitivity of CCD being 4 µV/e − . The integration test results show that the readout noise is 11.8 e − at 100 kHz readout pixel rate and the achieved energy spectrum resolution is 168 eV ± 4.7 eV (Full Width at Half Maximum: FWHM) at 5.9 keV.Index Terms-ASIC, CCD readout, incremental ΣΔADC, low noise.

Read-out circuit design of the X-ray detector

“…The data output can be implemented using the counting mode [7]. While programmable gain amplifiers (PGA) can achieve a larger integration range, they typically require more resources compared to ADC.A Sigma-Delta ADC can be utilized as the front-end readout circuit for detectors [8][9]. Sangwoo Lee et al designed a 16-bit switched-capacitor Sigma-Delta ADC as the readout circuit for an X-ray detector.…”