A fully integrated 10-bit 100 MS/s SAR ADC with metastability elimination for the high energy physics experiments

Cao, Shuxin; Wang, Chenxu; Zhang, Liang; Luo, Min; Yan, Wei; Gong, Yuehong

doi:10.1016/j.nima.2020.164415

Cited by 4 publications

(6 citation statements)

References 10 publications

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“…Tis structure may be divided into three stages: subarray capacitor, the MSB, MLSB and LSB as shown in Figure 11. High resolution and optimization of CDAC area Unlike in the merge-split technique as indicated in Figure 12, all capacitors on each side have been split into two similar capacitors except the dummy and unit capacitors [35][36][37]. Instead of handling the CDAC array, distribution of one capacitor splitting technique may be sufcient.…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…To improve the speed and power consumption of SAR ADC, an asynchronous scheme [7,11,16,17,24,35,44,53,58,64,86,91] is employed, as shown in Figure 35. Also, the complexity and area of SAR control logic are minimized.…”

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

“…Mainly, two parameters have been utilized to achieve power consumption reduction: decreasing the size of the capacitor array and using diferent level voltages. Te Scaled down reference [33] Scaled down reference [36] Monotonic [18] Monotonic [40] Charge redistribution [60] Two-step switching method [63] Charge sharing [22] Tri-level [65] Vcm-based [66] Hybrid [70] Hybrid [35] HSRS [73] Two energy saving [71] HSRS [76] Vaq-based [79] Vaq-based [31] Switching CDAC is suitable for the low-power SAR ADC. However, the diferent voltage switching schemes can improve the switching power consumption.…”

Section: Fom W � P Adcmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

Section: Fom W � P Adcmentioning

confidence: 99%

See 1 more Smart Citation

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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“…Introduction: SAR ADCs are widely used due to their medium-to-high resolution, low power consumption, and compact size [1][2][3][4]. Conventional asynchronous topology enables faster operation by the self-timed mechanisms [5][6][7][8], as shown in Figure 1a. These mechanisms comprise track-and-hold (T/H) and conversion periods [4], with the endpoint of each conversion dynamically determined for every sampling instance [5][6][7][8].…”

mentioning

confidence: 99%

“…Conventional asynchronous topology enables faster operation by the self-timed mechanisms [5][6][7][8], as shown in Figure 1a. These mechanisms comprise track-and-hold (T/H) and conversion periods [4], with the endpoint of each conversion dynamically determined for every sampling instance [5][6][7][8]. Typical asynchronous architectures require a high-frequency input clock to generate a predetermined T/H period [9,10], and each clock cycle also needs a margin to account for clock jitter [11].…”

mentioning

confidence: 99%

Asynchronous SAR ADC with self‐timed track‐and‐hold

Bae,

Lee,

Seong

et al. 2023

Electronics Letters

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This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases.

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Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

Tyagi,

Mittal,

Kumar

2023

Phys. Scr.

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The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

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A fully integrated 10-bit 100 MS/s SAR ADC with metastability elimination for the high energy physics experiments

Cited by 4 publications

References 10 publications

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Asynchronous SAR ADC with self‐timed track‐and‐hold

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

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