A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications

Ben-Bassat, Assaf; Gross, S.; Lane, A.A.; Nazimov, Anna; Khamaisi, Bassam; Solomon, Elad; Banin, Elan; Borokhovich, Eli; Kimiagorov, Nahum; Dinur, N.; Skliar, Phillip; Cohen, Roi; Banin, Rotem; Zur, Sarit; Reinhold, Sebastian; Breuer-Bruker, Smadar; Abuhazira, Tomer; Livneh, Tom; Maimon, Tzvi; Parker, Uri; Ravi, Ashoke; Degani, Ofir

doi:10.1109/jssc.2020.3024973

Cited by 22 publications

(10 citation statements)

References 19 publications

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“…It has been shown that polar architecture has an inherent power efficiency gain of up to 3 dB compared to the Cartesian architecture, due to the in-phase and quadrature (I/Q) signal summation in the latter [31]. Several successful designs and chip prototypes [32]- [36] have demonstrated the feasibility and superiority of the digital polar transmitters. Specifically, [32] demonstrated an analysis and implementation of a polar quantizer in a CMOS process for wireless receivers.…”

Section: ) Digital Transmitter Architecturesmentioning

confidence: 99%

Digital Polar Transmitters for Massive MIMO: Sum-Rate and Power Efficiency Analysis

Lampu

Kosunen

et al. 2024

IEEE Trans. Wireless Commun.

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In this article, we comprehensively investigate the potential of the digital polar radio transmitter architecture for multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) downlink system. In terms of throughput performance, we derive a lower bound for the average sum-rate achievable with Gaussian signaling inputs and zero-forcing (ZF) precoding based on Bussgang decomposition. By diagonal approximation, we derive an approximate, yet accurate, model for the distortion caused by uniform polar quantization, which can be used to evaluate the corresponding sum-rate in closed form. To assess the power efficiency, we provide power consumption models with realistic parameters and values for the quantized polar and Cartesian transmitters, based on state-of-the-art integrated circuit (IC) designs and measurements. Extensive numerical results demonstrate that the proposed quantized polar transmitter can enable excellent performance in terms of average sum-rate, symbol error rate (SER), and out-of-band (OOB) emission level, compared to the Cartesian architecture. Furthermore, the power consumption comparisons show that the digital polar transmitter can save more than 36% in the energy consumption under 64-antenna setting in typical 5G enhanced mobile broadband use cases, thus making it highly appealing for future power-efficient massive MIMO transmitter implementations.

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Section: ) Digital Transmitter Architecturesmentioning

confidence: 99%

Digital Polar Transmitters for Massive MIMO: Sum-Rate and Power Efficiency Analysis

Lampu

Kosunen

et al. 2024

IEEE Trans. Wireless Commun.

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“…For high linearity, analog PAs, i.e., Class-A and Class-AB PAs, have been widely used with limited efficiency [4], [5], [6]. On the contrary, digital PAs have been widely investigated in recent years for their merits of high efficiency and flexibility of operation modes [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32]. The switching unit cells contribute to the high efficiency of digital PAs.…”

Section: Introductionmentioning

confidence: 99%

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

Tang

Qian

Yang

et al. 2023

IEEE J. Solid-State Circuits

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This article presents a digital polar Doherty switched-capacitor power amplifier (SCPA) using on-chip selfcalibration technique with storage capacitor array (SCA) to compensate the amplitude modulation (AM)-phase modulation (PM) distortion automatically for high data-rate signals. Such a self-calibration technique detects the AM-PM distortion at output and generates the related phase compensation in PM signals. The SCA is proposed to store control voltages of phase shifter for different amplitude code and decrease the settle time for high data-rate, which achieves fast locking of the calibration loop. Based on the proposed self-calibration with SCA, a polar Doherty SCPA is designed and fabricated in conventional 40-nm CMOS technology. This chip achieves 28.9-dBm peak output power (P sat ) and 43.9% peak drain efficiency (DE) at 1.8 GHz. It supports 100-MHz 64-QAM/10-MHz 1024-QAM signal with 22.6-/21.3-dBm average output power and 33.9%/32.1% average DE without digital pre-distortion (DPD).

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“…Therefore, the increasing power consumption of mm-wave phased-array TRX is a critical issue. Digital TX provides improved system power efficiency by introducing a direct digital-to-RF modulation function [29], [30], [31], [32], [33]. Nonetheless, the design of phased-array TRX with direct digital-to-RF modulated TX suffers from concerns that the LO frequencies for RX and TX are different.…”

mentioning

confidence: 99%

A Phased-Array Transceiver With 2-Dimension Continuously Auto Link-Tracking Operation and Time Division Modulator

Luo,

Yang,

Deng

et al. 2024

IEEE J. Solid-State Circuits

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This work presents an eight-element 23-40 GHz continuously auto link-tracking phased-array transceiver (TRX) with a time division modulator in a conventional 40-nm CMOS technology. Such a TRX array can support fast auto-beamsteering in both receiver (RX) and transmitter (TX) arrays. The link-tracking loop is introduced to generate the phase and amplitude control codes of the RX array, which can automatically steer the RX beam to the unknown target direction to establish the RX link. After the RX link is located, the link-tracking loop provides a phase control code to steer the TX beam toward the target. Meanwhile, the time division modulator consists of four digital power amplifiers (DPAs), a quadrature signal generator, and a sign-map circuit. The time division modulator can not only tune the LO power for RX gain flatness improvement but also provide a baseband-to-RF direct conversion in TX mode. The measured link-tracking time and peak TX system efficiency are 7 µs and 25.3%, respectively, while the proposed TRX array can support 4.8 Gb/s 64-QAM and 8 Gb/s 16-QAM transmission.

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A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications

Cited by 22 publications

References 19 publications

Digital Polar Transmitters for Massive MIMO: Sum-Rate and Power Efficiency Analysis

Digital Polar Transmitters for Massive MIMO: Sum-Rate and Power Efficiency Analysis

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

A Phased-Array Transceiver With 2-Dimension Continuously Auto Link-Tracking Operation and Time Division Modulator

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