A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA in 0.5μm CMOS

Tang, Yi; Aktas, A.; Ismail, Mohammed; Bibyk, S.

doi:10.1109/mwscas.2001.986324

Cited by 13 publications

(10 citation statements)

References 7 publications

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“…The transmission gate (TG) is implemented using two CMOS, which can be used to form logic gates. Fig.4 shows a circuit for the divide-by-3/4 counter, which use TGs as logic gate and control logic for mode selection [16] . It has a higher speed by eliminating the delay introduced by NAND gate in critical path, and also has a lower power consumption by minimizing the number of full-speed DFF's in the first stage.…”

Section: Fig3 Schematic Diagram Of Conventional 4/5 Dividermentioning

confidence: 99%

Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

Liu

Zhang

Dai

et al. 2011

Optoelectron. Lett.

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Frequency synthesizer is an important part of optical and wireless communication system. Low power comsumption prescaler is one of the most critical unit of frequency synthesizer. For the frequency divider, it must be programmable for channel selection in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable division ratios. DMP is considered as a critical power dissipative block since it always operates at full speed. This paper introduces a high speed and low power complementary metal oxide semiconductor (CMOS) 15/16 DMP based on true single-phaseclock (TSPC) and transmission gates (TGs) cell. A conventional TSPC is optimized in terms of devices size, and it is resimulated. The TSPC is used in the synchronous and asynchronous counter. TGs are used in the control logic. The DMP circuit is implemented in 0.18 m CMOS process. The simulation results are provided. The results show wide operating frequency range from 7.143 MHz to 4.76 GHz and it comsumes 3.625 mW under 1.8 V power supply voltage at 4.76 GHz.Optical and wireless communication systems have been applied in many transmission interface recently. Frequency synthesizer is a major and critical component of optical and wireless transceiver. At high speeds and high pore densities, the power dissipation of optical transceivers becomes a critical element as it determines the type and size of package module. The complementary metal oxide semiconductor (CMOS) technology have the advantages of low cost and integration, and is widey used [1][2][3] . At GHz range, it is proven to be a good candidate for low power operation [4] .The phase-locked-loop (PLL) based architecture has become very popular for modern frequency synthesizer implementation [5,6] . Frequency dividers (FDs) also called prescalers. The prescaler is employed in the feedback path of the frequency synthesizer, taking a periodic signal and generating a periodic output signal whose frequency is a fraction of the input frequency. The prescaler is one of the most critical block in the frequency synthesizer, since it operates at the highest frequency and consumes large power. Thus the power reduction in the first stage of the prescaler is important in realizing a low power consumption frequency synthesizer.For the frequency divider, it must be programmable for channel-selection in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable frequeny-divided ratios [7,8] . In general, the high moduli is achieved by adding the flip-flops in the asynchronous counter at the cost of additional loading to the synchronous counter which results in degraded performance. The design of high speed prescalers similar processes with the frequencydividers [9,10] . How to design the low power consumption high speed prescaler is a challenging job.The purpose of this paper is designing a 15/16 DMP which has advantages of high speed and low power comsumption.The goal of an optical communication system is to carry large volumes of data across a l...

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Section: Fig3 Schematic Diagram Of Conventional 4/5 Dividermentioning

confidence: 99%

Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

Liu

Zhang

Dai

et al. 2011

Optoelectron. Lett.

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“…In the perspective of aggressive system integration, a broad-band frequency synthesizer that generates the local oscillator (LO) at all the required frequencies is a key block of a multistandard transceiver [1][2][3]. However more efficient solutions can be envisioned, taking advantage of the fact that different standards call for frequency synthesizers with different specifications.…”

Section: Introductionmentioning

confidence: 99%

“…We propose to realize the frequency multiplier using a PLL, whose VCO is based on a ring-oscillator, which is a good candidate for a compact solution with large tuning range. Since we can easily expect that a ring oscillator will have poor phase noise performance, the main contribution of this work is to prove the feasibility of a PLL that sufficiently rejects the VCO phase noise, in order to meet the WCDMA specifications that call for a phase noise level below À130 Ä À140dBc/Hz at a frequency offset between few megahertz and tens of megahertz [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

A local oscillator for WCDMA band VII based on frequency multiplication

Gerosa

Bevilacqua

Neviani

2012

Analog Integr Circ Sig Process

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This work explores the generation of a local oscillator for WCDMA band VII based on frequency multiplication of a GSM reference. The frequency multiplier is based on a PLL, which includes a compact VCO based on a ring oscillator. A proper PLL design allows to sufficiently reject the relative high VCO phase noise, complying with the WCDMA requirements. The effectiveness of the proposed approach is proved with the design of the whole multiplier in a 90 nm CMOS technology. The generated oscillation ranges from 3 to 6 GHz, while the simulated phase noise is −120 and −144 dBc/Hz at a frequency offset of 0.6 and 20 MHz, respectively, dissipating 6.3 mW

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“…vary with application. The conventional fractional-N PLLs mainly use one input data word providing hardware-fixed performance and thus lack in programmability [1][2][3][4][5][6]. In literature, there is scarcity of programmable architectures.…”

Section: Introductionmentioning

confidence: 99%

A Novel Architecture for Programmable Fractional-N PLL

Rana

2006

Analog Integr Circ Sig Process

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In this paper, a novel architecture for programmable fractional-N PLL is proposed. Unlike the conventional fractional-N PLL, it does not need any input data word to meet step size requirement. It features programmability in step sizes. The ratio of the externally controlled counter values sets the step size and thus step size is not limited by fixed hardware. A flow chart is provided to understand the operation of the various counters used in the proposed architecture. A behavioral modeling approach is attempted to perform overall system simulation using Hspice. A 2.4 GHz fractional-N PLL prototype is demonstrated using 0.35 µm CMOS process and test results are provided. It has step sizes of the values of integer multiples of 50 kHz. The main contributions include: (i) Novel architecture, and (ii) Prototype implementation, all for programmable fractional-N PLL. Unlike the most PLLs, the proposed PLL system is amenable to behavioral system simulation using Hspice.

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A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA in 0.5μm CMOS

Cited by 13 publications

References 7 publications

Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

A local oscillator for WCDMA band VII based on frequency multiplication

A Novel Architecture for Programmable Fractional-N PLL

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