A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver

Abstract

This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13 m CMOS technology. The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter. A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration. Pulse-swallow topology with a multistage noise shaping † modulator is adopted in the frequency divider design. The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes. Measurement results show that the phase noise of the synthesizer achieves-91.3 dBc/Hz and-117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset, separately. The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm 2 .

A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability

“…[12] Ref. [13] This Phase noise (dBc/Hz) -92 @ 100 kHz -95 @ 200 kHz -80 @100 kHz -93 @ 10 kHz -93 @100 kHz < 80 @100 kHz -115 @ 1 MHz -118 @ 1 MHz -115 @ 1 MHz -118 @ 1 MHz -117 @ 1 MHz -113 to -124 @ time achieves a constant loop bandwidth for each standard. Fabricated in a 0.18 m CMOS process, the synthesizer occupies an active area of 1.42 mm 2 and draws a current of 13.4-16.2 mA from a 1.8 V power supply.…”