A fully integrated power-management solution for a 65nm CMOS cellular handset chip

D'Souza, Arnold James; Singh, Ravpreet; Prabhu, J Raja; Chowdary, Gajendranath; Seedher, Ankit; Somayajula, S.; Nalam, Nageswara Rao; Cimaz, L.; Coq, Stephane Le; Kallam, Praveen; Sundar, Siddharth; Cheng, Shanfeng; Tumati, Sanjay; Huang, Wen‐Chang

doi:10.1109/isscc.2011.5746363

Cited by 9 publications

(4 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In multi-partition switching, the minimum pulse width of t on and t off can be restricted by the phase offset, t os , of switching signals. The t on range and the duty ratio range are calculated as (10) and (11), where n is the partitioned number. Therefore, the duty ratio range of the proposed multi-partition switching is from 0.016 to 0.984, and the limitation of output…”

Section: Active Principle Of Multi-partition Switching Techniquementioning

confidence: 99%

“…Meanwhile, the advancements of the semiconductor process and the circuit design techniques encourage the researches on system‐on‐a‐chip (SoC), which integrates various function blocks in a single chip. Most recently, the prestigious international journals and conferences have been presented to show the efforts to integrate the PMIC with various function blocks in the multimedia SoC [11, 12]. Power converters of the PMIC are divided into a linear regulator and a switching DC–DC converter according to the way to generate output voltages.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High‐efficiency low‐noise pulse‐width modulation DC–DC buck converter based on multi‐partition switching for mobile system‐on‐a‐chip applications

Ahn

Lee

2016

IET Power Electronics

View full text Add to dashboard Cite

This study presents a high-efficiency low-noise pulse-width modulation (PWM) DC-DC buck converter based on multi-partition switching for mobile system-on-a-chip applications. A multi-partition switching technique is employed for the control of large current driving switches to minimise the switching noise. In addition, a PWM control with a switching frequency of 2 MHz is applied for the driving of output stage with a heavy load to optimise the power efficiency. The prototype DC-DC buck converter with an active die area of 0.28 mm 2 was implemented using a 0.18 µm bipolar-CMOS-DMOS (BCD) process. The peak power efficiency is 93%, while supplying an output current of 200 mA and an output voltage of 1.8 V.

show abstract

Section: Active Principle Of Multi-partition Switching Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High‐efficiency low‐noise pulse‐width modulation DC–DC buck converter based on multi‐partition switching for mobile system‐on‐a‐chip applications

Ahn

Lee

2016

IET Power Electronics

View full text Add to dashboard Cite

show abstract

“…7. It is supplied with 5 V and based on standard low-voltage transistors in 65nm TSMC technology with a nominal voltage of 2.5 V (Dearn et al, 2005;D'Souza et al, 2011;Kuttner et al, 2011). Two-stacked pMOSs (PD1 and PD2) are used as pass transistors.…”

Section: System Descriptionmentioning

confidence: 99%

High-voltage circuits for power management on 65 nm CMOS

Pashmineh

Killat

2015

Adv. Radio Sci.

View full text Add to dashboard Cite

Abstract. This paper presents two high-voltage circuits used in power management, a switching driver for buck converter with optimized on-resistance and a low dropout (LDO) voltage regulator with 2-stacked pMOS pass devices. The circuit design is based on stacked MOSFETs, thus the circuits are technology independent.High-voltage drivers with stacked devices suffer from slow switching characteristics. In this paper, a new concept to adjust gate voltages of stacked transistors is introduced for reduction of on-resistance. According to the theory, a circuit is proposed that drives 2 stacked transistors of a driver. Simulation results show a reduction of the on-resistance between 27 and 86 % and a reduction of rise and fall times between 16 and 83 % with a load capacitance of 150 pF at various supply voltages, compared to previous work. The concept can be applied to each high-voltage driver that is based on a number (N) of stacked transistors.The high voltage compatibility of the low drop-out voltage regulator (LDO) is established by a 2-stacked pMOS transistors as pass device controlled by two regulators: an error amplifier and a 2nd amplifier adjusting the division of the voltages between the two pass transistors. A high GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. To improve stability, two feedback loops are utilized.In this paper, the 2.5 V I/O transistors of the TSMC 65 nm CMOS technology are used for the circuit design.

show abstract

“…Alternatively, significant process, voltage, and temperature (PVT) variations pose new stability challenges to the co-design of these ultra-small on-chip voltage regulators. Parallel voltage regulation where multiple regulators are connected to the same power grid has recently attracted significant attention, both from academia [21][22][23][24][25] and industry [26][27][28]. Satisfying small area, high power efficiency, and stability is however more challenging with parallel voltage regulation.…”

Section: Introductionmentioning

confidence: 99%

Distributed LDO regulators in a 28 nm power delivery system

P.-Vaisband

Price

Köse

et al. 2015

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

A fully integrated power delivery system with distributed on-chip low-dropout (LDO) regulators developed for voltage regulation in portable devices and fabricated in a 28 nm CMOS process is described. Each LDO employs adaptive bias for fast and power efficient voltage regulation, exhibiting 64 ps response time of the regulation loop and 99.49 % current efficiency. An adaptive compensation network is also employed within the distributed power delivery system to maintain a stable system response within 25 to 105°C and 10 % voltage variations with a capacitive load of more than 472 pF. No off-chip capacitors are required. Under a 788 mA load current step with 5 ns load edge, the power delivery system exhibits less than 15 % voltage droop for nominal input and output voltages, and a minimum dropout of 0.1 V. Each of the LDO regulators with the adaptive networks and bias current generator occupies 85 lm 9 42 lm in a 28 nm CMOS process. All of the test measurements are performed in a distributed power delivery system of six on-chip LDO regulators within a commercial high performance portable device. The proposed system is the first successful silicon demonstration of stable fully integrated parallel analog LDO regulators.

show abstract

A fully integrated power-management solution for a 65nm CMOS cellular handset chip

Cited by 9 publications

References 3 publications

High‐efficiency low‐noise pulse‐width modulation DC–DC buck converter based on multi‐partition switching for mobile system‐on‐a‐chip applications

High‐efficiency low‐noise pulse‐width modulation DC–DC buck converter based on multi‐partition switching for mobile system‐on‐a‐chip applications

High-voltage circuits for power management on 65 nm CMOS

Distributed LDO regulators in a 28 nm power delivery system

Contact Info

Product

Resources

About