A fully-integrated single-chip SOC for Bluetooth

Eynde, F. Op 't; Schmit, Joe; Charlier, V.; Alexandre, R.; Sturman, Charles; Coffin, K.; Mollekens, B.; Craninckx, Jan; Terrijn, S.; Monterastelli, A.; Beerens, S.P.; Goetschalckx, Paul; Ingels, Mark; Joos, D.; Guncer, S.; Pontioglu, A.

doi:10.1109/isscc.2001.912601

Cited by 54 publications

(7 citation statements)

References 1 publication

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“…The analog part is designed with differential structure that uses the single 1.8 V supply. The receiver uses the optimized Low-IF (1.5 MHz) architecture which is a trade-off between power and performance in CMOS technology [4], [7], [8]. This block uses the image rejection Gilbert mixer and the controllable AGC.…”

Section: Rf Transceiver and Basebandmentioning

confidence: 99%

A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform

Kim

Kim²,

Baek

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30 mm 2 in 0.18 μm CMOS, and the worst-case current of the total chip is 54 mA. key words: Bluetooth V2.0, enhanced data rate (EDR), low-power architecture, wireless SOC, sub band codec, platform-based design, verification

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Section: Rf Transceiver and Basebandmentioning

confidence: 99%

A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform

Kim

Kim²,

Baek

2010

IEICE Trans. Inf. & Syst.

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“…The bias currents of the delay cells are tuned according to the comparison result. After the calibration procedure is finished, the following equation can be satisfied: (10) where is the frequency of the reference signal. After the calibration mode, the MUX selects the IF2 and blocks the reference signal, and the demodulator starts to work at operation mode.…”

Section: B Implementationmentioning

confidence: 99%

A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

Chen¹,

Yang²,

Huang³

et al. 2009

IEEE Trans. Circuits Syst. I

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A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the transmitter, the open-loop VCO modulation is adopted to save hardware and power consumption. The transmitter frequency drift in open-loop modulation and frequency offset between the receiver and the transmitter can be easily resolved by the proposed receiver architecture. All required building blocks of the proposed transceiver, except a RF matching network and a crystal, were implemented on a 4-mm 2 chip by a 0.18-m CMOS process. The receiver achieves 89-dBm sensitivity at 0.1% BER with 1-Mb/s data rate, and the transmitter delivers up to 0-dBm output power. The receiver and transmitter consume 13.3 mA and 10.7 mA, respectively, from a 1.8-V power supply. Index Terms-Complex bandpass filter, demodulator, frequency synthesizer, low-noise amplifier (LNA), open-loop VCO modulation, time-to-digital converter (TDC).

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“…Phase errors as low as 3 • can be obtained due to process variations of the passive elements. 41,42,43 A drawback of this technique is that the higher the order of the polyphase network, the larger the insertion loss of the LO signal -3 dB of attenuation per stage. Another common technique for quadrature signal generation is the use of a VCO signal generated at twice the desired LO frequency.…”

Section: Quadrature Generationmentioning

confidence: 99%

Fully Integrated Frequency Synthesizers: A Tutorial

Moon

Valero-Lopez²,

Sánchez-Sinencio

2005

Int. J. Hi. Spe. Ele. Syst.

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Frequency synthesizer is a key building block of fully-integrated wireless communications systems. Design of a frequency synthesizer (FS) requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. The FS design challenge involves strong trade-offs, and often conflicting requirements. In this tutorial, the general implementation issues and recent developments of frequency synthesizer design are discussed. Simplified design approach should provide readers with sufficient intuition for fast design and troubleshooting capability. Open problems in this FS field are briefly discussed.

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A fully-integrated single-chip SOC for Bluetooth

Cited by 54 publications

References 1 publication

A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform

A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform

A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

Fully Integrated Frequency Synthesizers: A Tutorial

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