A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

Abstract

This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1 MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6 ls, at full load transition. The total ground current including the bandgap reference circuit is 28 lA and the active chip area measures 290 lm 9 360 lm in a 0.18 lm CMOS technology.

Full On-chip low dropout voltage regulator with an enhanced transient response for low power systems

“…In order to design a full on-chip LDO regulator, the number of compensating capacitors must be reduced [7]. Several LDO regulators suitable for on-chip integration have recently been designed [8][9][10][11][12][13][14][15][16][17][18][19]. However, existing solutions only partially address previously mentioned issues.…”

“…The compensation technique of the damping factor in [9] offers a high power supply rejection ratio (PSRR) (-30 dB at 1 MHz), but the regulator is not stable at a low load current. In [10], a symmetric single  ISSN: 2088-8708 Int J Elec & Comp Eng, Vol. 9, No.…”