A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching

Daoud, Luka; Latif, Muhammad Kamran; Jacinto, H S.; Rafla, Nader

doi:10.1016/j.micpro.2019.102919

Cited by 6 publications

(4 citation statements)

References 16 publications

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“…There also exists an FPGA implementation which handles the descriptor matching part after the keypoint extraction. 24 The architecture is fully pipelined and uses 16-bit fixed-point number representation.…”

Section: Related Workmentioning

confidence: 99%

Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

Fejér

Nagy

Benois‐Pineau

et al. 2021

Circuit Theory & Apps

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In this paper we describe an FPGA implementation of the Scale Invariant Feature Transform (SIFT) algorithm. The FPGA is required as its a lightweight device which makes it ideal for vision-guided hybrid neuro-prostheses utilised for upper limbs replacement. SIFT point detection is needed for computation of coordinates of the object-to-grasp in a wearable multi-camera system. A modified SIFT algorithm is proposed and an implementation of it into C/C++ language on Xilinx ZCU102 FPGA board. The proposed hybrid hardware/ software solution is compared to other hardware or hybrid implementations of the SIFT algorithm and with the baseline software detector OpenSIFT. The algorithm optimised for FPGA gives an average precision of 0.84 and the average recall of 0.94 in SIFT-point detection compared to the baseline.The proposed solution has lower dissipated power than other solutions like CPU or GPU, and it has better computational speed. This solution allows for processing medium-sized images in real-time with low power consumption.

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Section: Related Workmentioning

confidence: 99%

Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

Fejér

Nagy

Benois‐Pineau

et al. 2021

Circuit Theory & Apps

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“…The implementation of feature descriptors in the FPGAs remains an active research topic in recent years. Several works on fully pipelined FPGA accelerators for SIFT have been published since 2016 [30][31][32][33]. A parallel hardware architecture for SIFT was also reported in Reference [34].…”

Section: Comparison With Other Implementationsmentioning

confidence: 99%

Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA

2020

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Feature detection, description, and matching are crucial steps for many computer vision algorithms. These steps rely on feature descriptors to match image features across sets of images. Previous work has shown that our SYnthetic BAsis (SYBA) feature descriptor can offer superior performance to other binary descriptors. This paper focused on various optimizations and hardware implementation of the newer and optimized version. The hardware implementation on a field-programmable gate array (FPGA) is a high-throughput low-latency solution which is critical for applications such as high-speed object detection and tracking, stereo vision, visual odometry, structure from motion, and optical flow. We compared our solution to other hardware designs of binary descriptors. We demonstrated that our implementation of SYBA as a feature descriptor in hardware offered superior image feature matching performance and used fewer resources than most binary feature descriptor implementations.

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“…Traditional algorithms for object detection usually include scale-invariant feature transform (SIFT) [ 9 , 10 , 11 ], histogram of gradient (HOG) [ 12 , 13 ], and so on. Daoud et al [ 14 ] have proposed a fully pipelined hardware accelerator architecture for SIFT keypoint descriptor matching. Bakr et al [ 15 ] presented a method for action recognition by using the histogram of oriented depth gradients.…”

Section: Introductionmentioning

confidence: 99%

SAVSDN: A Scene-Aware Video Spark Detection Network for Aero Engine Intelligent Test

Kou

Zhang

Huang

et al. 2021

Sensors

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Due to carbon deposits, lean flames, or damaged metal parts, sparks can occur in aero engine chambers. At present, the detection of such sparks deeply depends on laborious manual work. Considering that interference has the same features as sparks, almost all existing object detectors cannot replace humans in carrying out high-precision spark detection. In this paper, we propose a scene-aware spark detection network, consisting of an information fusion-based cascading video codec-image object detector structure, which we name SAVSDN. Unlike video object detectors utilizing candidate boxes from adjacent frames to assist in the current prediction, we find that efforts should be made to extract the spatio-temporal features of adjacent frames to reduce over-detection. Visualization experiments show that SAVSDN can learn the difference in spatio-temporal features between sparks and interference. To solve the problem of a lack of aero engine anomalous spark data, we introduce a method to generate simulated spark images based on the Gaussian function. In addition, we publish the first simulated aero engine spark data set, which we name SAES. In our experiments, SAVSDN far outperformed state-of-the-art detection models for spark detection in terms of five metrics.

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A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching

Cited by 6 publications

References 16 publications

Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA

SAVSDN: A Scene-Aware Video Spark Detection Network for Aero Engine Intelligent Test

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