A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals

Limberg, T.; Winter, Markus; Bimberg, Marcel; Klemm, Reimund; Matúš, Emil; Tavares, M.B.S.; Fettweis, Gerhard; Ahlendorf, Hendrik; Robelly, P.

doi:10.1109/esscirc.2008.4681893

Cited by 25 publications

(15 citation statements)

References 11 publications

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“…Therefore, reusing the hardware resources can not only extend the processor application domain to handle other DSP applications beyond SDR, but also offer the possibility to integrate the two domain applications into a single processor, such as [2], [4]. Compared with high quality off-line video streams, the real-time video streams typically require much less processing power, so it is possible to share the processing elements between multimedia decoding and wireless baseband processing.…”

Section: Introductionmentioning

confidence: 98%

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor

Chen

Cao

et al. 2013

IEEE Trans. Signal Process.

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Recently, various specialized Software Defined Radio (SDR) baseband processors have been proposed for meeting the high performance and programmability requirements for emerging wireless communication applications. In order to support high throughput wireless communication, the SDR baseband processors typically employ many parallel computation elements, which may also be used for performing other signal processing applications. This paper explores the feasibility of performing complex media processing on such SDR baseband processors. Specifically, the full HD 1080p state-of-the-art H.264/AVC media decoding has been implemented onto a recent version of the ADRES based SDR baseband processor. Since the processor was originally designed exclusively for wireless baseband applications, algorithm and architecture co-optimizations are required to make the goal feasible. Following algorithm analysis, the computationally dominant tasks of the H.264/AVC, including the motion compensation, the intra prediction, the inverse integer transform, and the deblocking filter, have been selected to be mapped onto the ADRES. The experimental results show that, with limited architectural extensions, the ADRES based baseband processor achieves competitive performance efficiency, even compared with several processors that are specifically optimized for the media decoding application.Index Terms-Baseband processor, H.264/AVC decoder, full HD, SIMD.

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Section: Introductionmentioning

confidence: 98%

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor

Chen

Cao

et al. 2013

IEEE Trans. Signal Process.

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“…A hardware implementation of a run-time scheduler with excellent performance but suffering from poor flexibility was introduced in [2]. In [3], a queue-based scheduling unit for a base station, called Multicore Navigator, is introduced.…”

Section: Introductionmentioning

confidence: 99%

Towards elastic SDR architectures using dynamic task management

Arnold

Matúš

Noethen

et al. 2013

2013 IEEE Global Conference on Signal and Information Processing

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SDR platforms integrating several types and numbers of processing elements in System-on-Chips become an attractive solution for baseband processing in wireless systems. In order to cope with the diversity of protocol applications and the heterogeneity of multi-core architectures, a hierarchical approach for workload distribution is proposed in this paper. Specifically, a system-level scheduler is employed to map applications to multiple processing clusters, complemented with a cluster-level scheduler -the CoreManager -for dynamic resource allocation and configuration as well as for task and data scheduling. A performance analysis of the proposed approach is presented, which shows the advantages of dynamic scheduling against a static approach for variable workloads in the LTEAdvanced uplink multi-user scenarios.

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“…Results for two supply voltages are reported for a Method 2 decoder: 1.3 and 0.7 V. (Note that, at 0.7 V, for max = 15, the 1 This work is also a variant of Split-Threshold method. 2 Throughput is computed based on the maximum latency reported. 3 Power numbers are for = 6, Method 2.…”

Section: Comparison With Othersmentioning

confidence: 99%

“…Local and cellular wireless communication throughputs are expected to increase to hundreds of Mbps and even beyond 1 Gbps [1][2][3]. With this increased growth for bandwidth comes larger systems integration complexity and higher energy consumption per packet.…”

Section: Introductionmentioning

confidence: 99%

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Shirani-Mehr

Baas

2013

VLSI Design

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An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm 2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6× lower than the state of the art reported power with an SNR loss of 0.35 dB at BER = 10 −7 .

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A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals

Cited by 25 publications

References 11 publications

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor

Towards elastic SDR architectures using dynamic task management

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

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