A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse

Abstract

This paper proposes a fully synthesizable digital lowdropout (DLDO) regulator using an automatic offset control and reuse technique implemented in a 65-nm CMOS technology. To realize the fully synthesizable DLDO design, all components of core blocks are made with standard logic cells. The proposed offset control and reuse technique is adopted to cancel the offset voltage from the logic cells automatically, to provide the adaptive equivalent thresholds for the voltage comparison window, and to speed up the dropout voltage response. Besides, the modified comparator-triggered oscillator introduces the output of the comparator to the oscillation loop to choose the optimum clock edge in the delay line to feed back, which ensures both of the fast response and enough time margin for the comparator delay at the same time. The core area of the output-capacitance-less DLDO is 0.027 mm 2 . The simulated results show that a 100 mA step in load current produces a voltage drop of 140 mV with the response time of 1.2 ns. The steady-state error is less than 4 mV. The peak current efficiency is 99.9%.

A 540-mA, 0.0487-ps-FOM Digital LDO based on Bi-directional Binary Search with Dual-loop Control

“…The digital LDO outputs a well regulated variable voltage ranging from 0.6 V to 1.3 V, providing a maximum load current of 540 mA with 99.99% current efficiency. [11] are calculated by equation ( 6) and ( 7), which produces 0.0487 ps and 0.0219 pF respectively for the proposed design. The FOMs and current efficiency of the proposed LDO is better than the state of art.…”

“…Based on it, a double-edge regulation was proposed in [9], where half of the D flipflops (DFFs) operate on the rising edge and the rest on the falling edge, reducing the response time by half. To further improve the response speed, adaptive CLK generation (ACG) is utilized in [10] [11] at the cost of power consumption.…”

“…The digital LDO attains low quiescent current consumption, low undershoot and fast transient response. The commonly used figure of merits (FOMs)[11] are calculated by equation (6) and (7), which produces 0.0487 ps and 0.0219 pF respectively for the proposed design. The FOMs and current efficiency of the proposed LDO is better than the state of art.…”

A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

“…In this design approach, all circuit building blocks are implemented through standard-cells taken from the digital library and coded in a hardware description language, which can then be synthesized from commercial standard-cell libraries and automatically placed and routed using electronic design automation (EDA) tools. Compared to conventional analog implementations, standard-cell-based analog implementations significantly shorten the design time and cost [20][21][22][23][24][25][26][27][28][29][30][31][32].…”