A functional block decomposition method for automatic op-amp design

Automatic generation of macromodels and design equations for application to Op Amp design

“…Making full automation of such academic tools still requires advanced knowledge‐acquisition algorithms. Circuit recognition can offer many benefits to the existing symbolic analysis methods and analog automation methods as explored previously by Massier et al 3 and Abel et al 4 Based on recognition, we can automatically partition a circuit into smaller components and create macromodels or partial sizing constraints in correspondence to the functional circuit blocks. Based on a partitioned circuit, symbolic analysis complexity can be substantially reduced. Moreover, compact symbolic results can be generated using smaller functional circuit blocks with better interpretability. Considering that the popular gm/ID design method can take advantage of ad hoc functional cells, we anticipate that recognized circuit cells can be utilized by grouping transistors, thereby enhancing the efficiency of a gm/ID‐based sizing optimization schemes by searching a lower dimensional state space. …”

“…The feasibility of these expectations has to be based on the fact that CMOS Op Amps are formed with layered functional circuit blocks; an experienced human designer can easily recognize them just by visual inspection. However, we have not seen so far much research effort on addressing automatic recognition of functional circuit cells, except for Massier et al 3 and Abel et al, 4 which are targeted at generating sizing constraints and topological circuit synthesis, but not for symbolic model generation and design equation generation addressed in this work. Normally, developing a specific circuit recognition scheme should be bound to the subsequent application needs.…”

“…Circuit recognition for generating symbolic macromodels automatically would require quite different implementation techniques from that developed for extracting sizing constraints and developing synthesis cell libraries. The mathematical set‐based description language developed by Abel et al 4 cannot directly suit our purpose in this paper.…”

“…We point out that, although Abel et al's work 4 also considered extraction of gain stage transconductance and output conductance, and so forth, their basic intention was not to combine with a symbolic analysis tool for generating design equations such as the pole‐zero equations. A key requirement on PZ generation is that created macromodel bear topological resemblance to the original transistor‐level circuit so that expressions of PZ could carry circuit element information easily localizable to specific circuit cells.…”

“…But how to implement circuit partitioning effectively to cope with a variety of application needs remains a research subject. Existing methods as presented in Massier et al 3 and Abel et al 4 were dedicated to deriving constraints for sizing and synthesizing simple topology circuits, but not targeted at generating macromodels for appraising sophisticated circuits. As a matter of fact, issues such as determining functional cells of an analog circuit to facilitate design knowledge acquisition are nontrivial and yet to be resolved in order to incorporate symbolic methods in an analog design automation flow 5 …”