A Fundamental Study of Ultrahigh-Speed Hardware Architecture for Particle Swarm Optimization

Abstract

Particle swarm optimization (PSO) is a powerful method for dealing with the optimization of nonlinear applications such as network optimization, power system optimization and so on. The PSO algorithms enable a higher signal processing speed than conventional approaches and dedicated digital signal processor (DSP) in various application fields. However, the software implementation of PSO is extremely time-consuming when the numbers of iterations and particles become large. In some applications such as smart engine control, nuclear reactor control and so on, real-time control on the order of μm-ms is required, which is extremely difficult to achieve in an embedded system. To realize ultrahigh-speed signal processing of the aforementioned applications, several possible approaches of PSO hardware implementation are discussed and investigated in this paper. A novel hardware architecture for the PSO algorithm is employed to overcome the above difficulties. In this research, the proposed hardware architecture is implemented into a field-programmable gate array (FPGA) to evaluate its performance. The proposed hardware architecture employs two features, which are a serial architecture with two-level pipelines and an adaptive generic particle calculation block (AGPCB). It can not only achieve much faster performance than the conventional approaches but also minimize the chip cost simultaneously. The related research achievements prove that the proposed hardware architecture can greatly reduce the calculation time while achieving high efficiency. In addition, the proposed approach has compatibility with various PSO algorithms to meet the requirements of different nonlinear applications.