A Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard

Rupanagudi, Sudhir Rao; J, Valliveti Vidya; Bhat, Varsha G.; Padmavathi, P.; G, Darshan; Gurikar, Shreya K.; Darshan, S; Sindhu, N.

doi:10.1109/kst.2019.8687545

Cited by 9 publications

(3 citation statements)

References 19 publications

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“…AES cryptosystem can be used effectively to protect sensitive data, while it is at rest, or during transmis-sion between different entities. Several approaches have been developed to enhance the efficiency of AES cryptosystems as in (Oukili and Bri, 2017, Rao Rupanagudi et al, 2019, Langenberg et al, 2020. AES cryptosystems have been applied in various domains, such as healthcare and smart grids, to ensure the confidentiality of sensitive data.…”

Section: Literature Reviewmentioning

confidence: 99%

Introduction to the Special Issue on Software-Intensive Autonomous Systems: Methods and applications

Drira

Rodriguez

Khabou

et al. 2023

Journal of Systems and Software

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Section: Literature Reviewmentioning

confidence: 99%

Introduction to the Special Issue on Software-Intensive Autonomous Systems: Methods and applications

Drira

Rodriguez

Khabou

et al. 2023

Journal of Systems and Software

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“…Researchers have also worked on AES in terms of performance and security, both in hardware and software. Tillich and Herbst [35], Rupanagudi et al [36], Moh'd [37], Talha [38], and Shreedhar et al [39] proposed a method for improving the performance of AES in hardware in terms of area and clock speed. Intel's corporation proposed new AES instruction set for improving its performance and security for their processors [40].…”

Section: Introductionmentioning

confidence: 99%

Generation of Highly Nonlinear and Dynamic AES Substitution-Boxes (S-Boxes) Using Chaos-Based Rotational Matrices

et al. 2020

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This work reports a novel chaos-based affine transformation generation method, which is based on rotational matrices to design strong key-based S-boxes. Chaotic logistic map's nonlinear trajectories are used to generate rotational matrices under given design conditions. Thus, the inherent logic is to generate key-based S-boxes, as strong as AES S-box, in terms of cryptographic properties using chaos in affine transformation. The randomness of chaotic sequences is tested using the National Institute of Standard and Technology (NIST) Statistical Test Suit (STS) 800-22 that validates the generated sequences for S-box design. The results show that methodology adapted to design proposed key-based dynamic S-boxes entails near-optimal cryptographic properties so that proposed S-boxes are as stronger as AES S-box. INDEX TERMS Affine transformation, chaotic logistic map, S-box, NIST test.

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“…et al,2013) and implemented a Vedic Mathematics multiplier on FPGA. Since then, several authors have been implementing Vedic Mathematics based multipliers in several applications related to the fields of communication, cryptography and DSPs (S. R. Rupanagudi et al,2014;S. Rao Rupanagudi et al, 2019).…”

Section: Introductionmentioning

confidence: 99%

Design of 128-bit Complex Number Multipliers for Co-Processor

Panda¹

2020

Biosci. Biotech. Res. Comm

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Multipliers are the backbone of high-performance computing systems such as Microprocessors and Digital signal processors. Multipliers require more hardware resources and processing time, hence they are the slowest elements in the system. Multipliers are mainly used in today's high-end Digital Signal Processors and they occupy a larger chip area because of their inherent internal circuit complexity. Present-day co-processors are designed to support different size computations to achieve high performance. Researchers have worked on signed and complex number multipliers used in co-processors of 64 bit and below. There is a scope for designing a higher bit complex number multiplier to achieve higher performance. In this context, we proposed to design of 128-bit complex number multiplier of various architectures such as Booth Multiplier, Modified Booth Multiplier, Urdhva Multiplier and Nikhilam Multiplier using ModelSim SE 6.4 and Xilinx Vivado. In this work, various architectures such as Booth Multiplier, Modified Booth Multiplier, Urdhva Multiplier and Nikhilam Multiplier for 8-bit, 16-bit, 32-bit, 64-bit and 128-bit designed using Verilog for complex number multiplication. Nikhilam is one of the sutras of Vedic mathematics which is chosen for the implementation of complex number multiplier for area reduction. Synthesis reports are generated using the Xilinx Vivado tool for speed and power comparison. From the comparison, we have observed that Booth, Modified Booth, Urdhva, and Nikhilam occupy an area of 324.32%, 292.79%, 56.36%, and 46.70% respectively for 128-bit implementations. Among all the implemented methods, the Nikhilam method for complex number multiplier occupies very less area i.e. only 46.70% on-chip area.

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A Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard

Cited by 9 publications

References 19 publications

Introduction to the Special Issue on Software-Intensive Autonomous Systems: Methods and applications

Introduction to the Special Issue on Software-Intensive Autonomous Systems: Methods and applications

Generation of Highly Nonlinear and Dynamic AES Substitution-Boxes (S-Boxes) Using Chaos-Based Rotational Matrices

Design of 128-bit Complex Number Multipliers for Co-Processor

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