A Gate Level Methodology for Efficient Statistical Leakage Estimation in Complex 32nm Circuits

Abstract

Abstract-A fast and accurate statistical method that estimates at gate level the leakage power consumption of CMOS digital circuits is demonstrated. Means, variances and correlations of logic gate leakages are extracted at library characterization step, and used for subsequent circuit statistical computation. In this paper, the methodology is applied to an eleven thousand cells ST test IP. The circuit leakage analysis computation time is 400 times faster than a single fast-Spice corner analysis, while providing coherent results.

Energy study for 28nm FDSOI technology

“…Simulations Regarding leakage power, to estimate the leakage of benchmark circuits, we adapted the method developed by [7] to a 28 nm FDSOI technology and aimed to improve it. The flow of this method is devised in two parts as shown in Figure 2.…”