A gate-quality dielectric system for SiGe metal-oxide-semiconductor devices

Abstract

The use of Si,-, & , alloys for p-channel hightransconductance MOSFET's requires a high-quality dielectric system. Direct oxidation of Si,-,Ge, alloys or even lowtemperature deposition of SiO, directly on Si, -, & , results in a very high interface state density. We show that the use of a thin (6-8 om) Si cap layer grown epitaxially on the Si,-,Ge, layer with the subsequent plasmaenhanced chemical vapor deposition of silicon dioxide gives low (below 10" eV -' * em-,) interface state density. The Si cap layer leads to a sequential turn-on of the Si,-,&, channel and the Si cap channel, as clearly observed in the low-temperature CV curves. We show that this dualehannel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets.

MOS gated Si:SiGe quantum wells formed by anodic oxidation

“…Unfortunately, the growth of conventional (high-temperature) thermal oxides on Si:SiGe can lead to material degradation due to strain relaxation, dopant and Ge diffusion, or the propagation of dislocations [1][2][3]. To address these problems a variety of methods have been used to grow low-temperature oxides on both Si:SiGe [3][4][5] and SiGe [6][7][8]. In this letter we report on the first attempt to grow a low-temperature oxide on Si:SiGe using electrochemical anodic oxidation.…”

Design and optimization of a buried channel PMOS integrable in a Si1−xGex BiCMOS process

“…This is because as the gate voltage becomes negative, initially inversion occurs in the buried SiGe channel, and the capacitance is [10,30,35]. Here it indicates that the band offsets have been simulated correctly in device simulation.…”

“…On the other hand, for thinner caps, the interface state density at the Si-SiO 2 interface increases [30]. It is not possible to include this effect in device simulation.…”

“…Thus, there is a trade-off with the cap layer thickness. A cap thickness down to 6-8 nm gives low values of D it [30], and thus is a good compromise between hole confinement and mobility. In one study, a 2.3 nm thick cap layer was found give minimal parasitic conduction in the Si cap layer [32].…”

Band-Structure and Quantum Effects on Hole Transport in p-MOSFETs

“…Hole transport is affected by the warping and anisotropy of the valence bands and as such hole mobility in Si inversion layers is lower than the electron mobility by about a factor of three [1]. Several alternate device structures aimed at boosting the speed and density of VLSI circuits have been suggested to improve hole transport in such structures [2][3][4]. The important ones are surface channel strained Si [5] and buried channel strained SiGe p-channel MOSFETs.…”