A gated clock scheme for low power scan testing of logic ICs or embedded cores

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

“…Over the years, numerous techniques for test power reduction in shift and capture modes have been proposed, including test scheduling [9], test vector reordering [10], partitioning [11], X-fills [12][13][14], blocking gate [15][16][17][18][19], and clock gating [20][21][22][23], etc. In general, an ideal test power reduction strategy should include the following properties:…”

Scan Architecture With Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction

“…After the first capture clock (scan clk[0] = 00100), the first third of the circuit response is latched into Segment 0, in the second capture clock (scan clk [1] = 00100), another third of the test response is stored into Segment 1, and in the third and last capture clock (scan clk [2] = 00100), the last part of the circuit response is stored into Segment 2. The multiclock capture cycle is the fundamental 1 One possible solution for making the scan control unit testable is to scan its sequential part, i.e., the flip-flops of the modulo-N counter, and add observation difference between this approach and all previously proposed low power scan architectures, which capture the entire test response in a single clock. While in the case of single-clock capture, all flip-flops in the scan chain can change their values simultaneously, the multiclock capture cycle allows at most 1=N of the flip-flops in the design to change their value simultaneously.…”

“…The method proposed in [1] uses two nonoverlapping clocks running at half the frequency of the main clock to operate the odd and the even scan cells of the scan chain. This technique reduces shift-power dissipation by a factor of approximately two, without affecting the testing time or the performance of the circuit.…”

“…Methods based on scan chain partitioning [1], [10], [16], [20] appear to be efficient solutions in terms of shift-power reduction and integrability into existing design flows versus area and testing time overhead, when compared to other approaches. Hence, these methods merit further investigation and provide the foundation for the work presented in this paper.…”

“…Scan chain partitioning [1], [10], [16], [20]. The method proposed in [1] uses two nonoverlapping clocks running at half the frequency of the main clock to operate the odd and the even scan cells of the scan chain.…”